I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
Similar Posts
How to create a timer in VHDL
In earlier tutorials we have used the wait for statement to delay time in simulation. But what about production modules? The wait for statement cannot be used for that. That only works in simulation because we can’t just tell the electrons in a circuit to pause for a given time. So how can we keep…
Getting started with VUnit
VUnit is one of the most popular open-source VHDL verification frameworks available today. It combines a Python test suite runner with a dedicated VHDL library to automate your testbenches.
FPGA course – Everything you need to know about the Dot Matrix VHDL Course
I’m excited to announce that the VHDL and FPGA course that I have been working on for the last six months is starting to become complete. The course is in beta at the moment, and I am planning on launching it for the first time this autumn. Who is the FPGA course for? The FPGA…
How to delay time in VHDL: Wait For
In the previous tutorial we learned that a process can be thought of as a program thread. We also learned that a wait; statement causes the program to pause indefinitely. But is there a way to make a program wait for any other time value than forever? If we remove the wait; altogether and try…
An Introduction to FPGAs & Programmable Logic
This video is an introductory presentation about FPGA and programmable logic technology. I delivered this 45 minutes talk at an event hosted by 7 Peaks Software in Bangkok, Thailand, on November 19th, 2019.
Stimulus file read in testbench using TEXTIO
Reading signal values from file is an alternative way of generating stimuli for the device on test (DUT). The testbench sequence and timing is hard-coded in a stimulus file that is read by the VHDL testbench, line by line. This allows you to easily change the pattern of the waveform that you want to feed…
First of all, thank you so very much!
These are by far the most comprehensible tutorials I have come across like ever!
Brilliant work.
So here my two cents out of gratitude:
Basic VHDL Quiz – part 4
Which statement is not true?
Answer 3 : The return statement cannot be omitted.
-> Correct
So the return statement CAN be omitted???
“Unlike in most other programming languages, the return keyword is mandatory in functions in VHDL.”
Confused by double negation. Me or you 😉
Good catch! I’ve changed the answer now. I was trying to make you think, but in the process I confused myself too 🙂
“The return-keyword cannot be used in a procedure”. I believe that this is incorrect, e.g.
https://web.archive.org/web/20200629023040/http://vhdl.renerta.com:80/source/vhd00060.htm
It is true, of course, that you cannot return a value with it, that’s the only (?) difference between procedures and functions. But, as in other languages, you can use “return” as control flow statement to “force an exit”.
You are right! I missed the possibility of using return statements in procedures without returning a value. According to the Renata link you posted, functions must return a value, while procedures can have return statements, but then without a return value.
I am changing this question.