# VHDLwhiz > VHDLwhiz is a learning site for VHDL and FPGA design, run by Jonas Julian Jensen, a Norwegian FPGA engineer who spent years in the aerospace industry before turning to teaching full-time. The site covers the VHDL language, simulation, synthesis, and verification, along with the day-to-day workflows of building production FPGA designs across the AMD (Xilinx), Altera (Intel), and Lattice toolchains. It is VHDL-specific and does not cover Verilog or SystemVerilog. The site is ad-free, supported entirely by paid courses and the VHDLwhiz Membership program. The content is built around working code. Tutorials ship with downloadable simulator projects you can run yourself. Verification material covers self-checking testbenches and the open-source frameworks engineers reach for in practice: UVVM, OSVVM, VUnit, and Cocotb. Free content includes the 23-lesson Basic VHDL Course, a glossary of VHDL and FPGA terminology, a snippet library of reusable code patterns, and interactive VHDL quizzes. Reference material covers all VHDL attributes and the IEEE and STD library package declarations, alongside a deep archive of free articles and YouTube videos covering everything from `std_logic` types to FIR filters. Paid content is centered on the VHDLwhiz Membership, a subscription portal with 40+ courses and a library of example designs, testbenches, templates, scripts, and coding challenges. Flagship courses like Dot Matrix and the FPGA and VHDL Fast-Track are also sold individually outside the Membership. --- ## Start here - [VHDLwhiz - The best resource for VHDL engineers](https://vhdlwhiz.com/): VHDLwhiz's courses, articles, and resources help you learn and understand advanced concepts within FPGA design using VHDL. - [Basic VHDL Course](https://vhdlwhiz.com/basic-vhdl-tutorials/): A beginners VHDL tutorial which gets you started programming VHDL. No hardware is required, exercises are run in the ModelSim VHDL simulator. - [Articles](https://vhdlwhiz.com/articles/): Index of all VHDLwhiz articles and tutorials. - [Free VHDL resources](https://vhdlwhiz.com/free-resources/): Here's a collection of free VHDL and FPGA training resources by VHDLwhiz. Start with the free course and click your way around to learn more! - [Shop](https://vhdlwhiz.com/shop/): The VHDLwhiz shop contains the free and premium courses and downloadables. - [About](https://vhdlwhiz.com/about/): Who am I? I’m Jonas from Norway. Before I started working full-time on VHDLwhiz, I worked as an FPGA engineer in the aerospace industry. - [Contact](https://vhdlwhiz.com/contact/): Get in touch with VHDLwhiz! Send me an email or use the contact form. --- ## Other pages - [Reconfigurable FPGA Accelerator for Databases](https://vhdlwhiz.com/reconfigurable-fpga-accelerator-for-databases/): This thesis proposes a novel approach to utilize dynamic partial reconfiguration in FPGAs for processing arbitrary SQL queries in hardware. --- ## Articles - [UVVM results in faster and better FPGA verification](https://vhdlwhiz.com/uvvm-faster-fpga-verification/): How UVVM lets FPGA designers control multiple interfaces simultaneously in VHDL testbenches, reducing verification time and catching more bugs. - [NAND logic gates interactive demo](https://vhdlwhiz.com/nand-logic-gates-interactive/): NAND gates alone can implement any Boolean function. Play with the switches to see how NOT, AND, OR, NOR, XOR, and XNOR gates are realized in NAND logic. - [NOR logic gates interactive demo](https://vhdlwhiz.com/nor-logic-gates-interactive/): NOR is a universal gate. You can construct any other logic gate from it. See how to build NOT, AND, NAND, OR, NOR, XOR, and XNOR with NOR logic. - [Open Logic - An FPGA Standard Library](https://vhdlwhiz.com/open-logic-fpga-standard-library/): Open Logic is an open-source VHDL library of vendor-independent FPGA components like FIFOs, CDCs, and interfaces, designed to save you time. - [ASCII table](https://vhdlwhiz.com/ascii-table/): Table of ASCII and Latin-1 characters with decimal, hex, and binary values, plus the VHDL character type enumeration literals. - [Logic gates interactive demo](https://vhdlwhiz.com/logic-gates-interactive/): The logic gates NOT, AND, NAND, OR, NOR, XOR, and XNOR are fundamental building blocks in digital circuits corresponding to Boolean operators. - [Part 6: Complementary FIR filters](https://vhdlwhiz.com/part-6-complementary-fir-filters/): Learn what complementary (FIR) finite input response filters are and the considerations you must take to implement them in FPGAs. - [Part 5: Polyphase FIR filters](https://vhdlwhiz.com/part-5-polyphase-fir-filters/): Discover polyphase FIR filters in DSP systems. Learn about interpolation, decimation, optimization techniques, and more in this guide. - [Part 4: FIR filter testing](https://vhdlwhiz.com/part-4-fir-filter-testing/): Here are some testing procedures and verification techniques to ensure your FIR (finite impulse response) filters are working correctly. - [Should I learn VHDL if Verilog is becoming more popular?](https://vhdlwhiz.com/should-i-learn-vhdl-if-verilog-is-becoming-more-popular/): Is VHDL or Verilog more used? Which HDL should I learn to get an FPGA designer job? Let me help you find answers to these questions! - [Function and procedure call overhead in VHDL](https://vhdlwhiz.com/function-and-procedure-call-overhead-in-vhdl/): Let's find out if function and procedure calls in VHDL are bad for synthesis, implementation, or timing and if it slows down the simulation. - [How the AXI-style ready/valid handshake works](https://vhdlwhiz.com/how-the-axi-style-ready-valid-handshake-works/): The ready/valid protocol uses a simple hardware bus handshake. Data only transfers when ready and valid are '1' during the same clock cycle. - [Short-circuit operations in VHDL](https://vhdlwhiz.com/short-circuit-operations-in-vhdl/): For some Boolean logic operators and data types, VHDL simulators skip the right-hand operand if the left-hand operand has certain values. - [Operator precedence in VHDL](https://vhdlwhiz.com/operator-precedence-in-vhdl/): VHDL uses this table of precedence classes to determine the order of operations when evaluating mathematical or logical expressions. - [How to define and print multiline string literals in VHDL](https://vhdlwhiz.com/define-and-print-multiline-string-literals-in-vhdl/): Learn how to split long code lines, concatenate strings, add line feed characters to string literals, and print strings using VHDL. - [Part 3: FIR filter types](https://vhdlwhiz.com/part-3-fir-filter-types/): This article explains the most popular FIR structures for FPGA implementation. Learn about the pros and cons of the different filter types. - [Part 2: Finite impulse response (FIR) filters](https://vhdlwhiz.com/part-2-finite-impulse-response-fir-filters/): The FPGA designer can implement the FIR filter either parallel or in series. Learn how to create a FIR filter using VHDL. - [Part 1: Digital filters in FPGAs](https://vhdlwhiz.com/part-1-digital-filters-in-fpgas/): Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) are the two types of digital filters you’re most likely to use in FPGAs. - [Using the 'stable and 'quiet attributes in VHDL](https://vhdlwhiz.com/stable-and-quiet-attributes/): The difference between 'stable and 'quiet is that 'stable only considers signal value changes, while 'quiet senses all signal assignments. - [How to link Quartus Prime IP libraries to VUnit](https://vhdlwhiz.com/link-quartus-ip-libraries-to-vunit/): This tutorial shows you how to generate, incorporate, and link an external IP core from the Quartus IP libraries to a VUnit VHDL testbench. - [The ModelSim commands you need to know](https://vhdlwhiz.com/the-modelsim-commands-you-need-to-know/): When you press a button in the ModelSim GUI, it runs a command backend. These are the command you need to know to compile and simulate. - [Getting started with VUnit](https://vhdlwhiz.com/getting-started-with-vunit/): VUnit is an open-source VHDL verification framework that automates your testbenched with a Python test suite runner and a VHDL library. - [Formal verification in VHDL using PSL](https://vhdlwhiz.com/formal-verification-in-vhdl-using-psl/): Formal verification techniques can help you map a requirement to a test, proving that your VHDL module conforms to the specification. - [Using Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO)](https://vhdlwhiz.com/using-ila-and-vio/): This tutorial covers using Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO) to debug and monitor your VHDL design in Vivado. - [Free VHDL simulator alternatives](https://vhdlwhiz.com/free-vhdl-simulator-alternatives/): There are many free, legal VHDL simulators that you can download and install on Windows, Linux, or even Mac OS. ModelSim is the most popular. - [How to create a list of strings in VHDL](https://vhdlwhiz.com/string-list/): A regular string array in VHDL is limited to fixed-length text strings. But we can create a Python-style string list using protected types. - [Why latches are bad and how to avoid them](https://vhdlwhiz.com/why-latches-are-bad/): A latch is an undesirable logic element in an FPGA. Latches put strains on the router and offer no added benefit compared to flip-flops. - [Configuration constructs explained](https://vhdlwhiz.com/configuration-constructs-explained/): Configurations are useful for maintaining multiple design versions. The example shows how to replace a component instantiation in VHDL. - [Entity instantiation and component instantiation](https://vhdlwhiz.com/entity-instantiation-and-component-instantiation/): See examples of the two ways to instantiate a VHDL module: component instantiation and entity instantiation (direct instantiation). - [Generate statement debouncer example](https://vhdlwhiz.com/generate-statement/): The generate statement in VHDL can automatically duplicate a block of code to closures with identical signals, processes, and instances. - [RC servo controller using PWM from an FPGA pin](https://vhdlwhiz.com/rc-servo-controller-using-pwm/): This tutorial shows how to create a PWM controller for an RC servo using VHDL. We test it on the Lattice iCEstick FPGA board with the TowerPro SG90 servo. - [How to create a Tcl-driven testbench for a VHDL code lock module](https://vhdlwhiz.com/tcl-driven-testbench-for-vhdl-code-lock-module/): This tutorial shows how to create a Tcl-driven testbench in ModelSim. The Tcl-based testbench will check that a VHDL "code lock" module works correctly. - [How to stop simulation in a VHDL testbench](https://vhdlwhiz.com/how-to-stop-testbench/): Learn how to end a VHDL simulation that completes successfully using the VHDL keywords: finish, stop or assert. You can also stop the testbench using Tcl. - [Clk'event vs rising_edge](https://vhdlwhiz.com/clkevent-vs-rising_edge/): While rising_edge(clk) and clk'event and clk = '1' are equivalent when implemented on the FPGA, the two statements may behave differently in simulation. - [Make Lattice iCEcube2 work on Ubuntu 20.04 and program the iCEstick FPGA board](https://vhdlwhiz.com/lattice-icecube2-ubuntu-20-04-icestick/): This tutorial shows how to install the Lattice iCEcube2 FPGA design software on Ubuntu 20.04 and how to program the iCEstick FPGA from Ubuntu Linux. - [How to create a breathing LED effect using a sine wave stored in block RAM](https://vhdlwhiz.com/breathing-led-using-sine-wave-stored-in-block-ram/): Learn how to generate a sine wave in an FPGA using VHDL. See how to use block RAM as a lookup table to create a LED breathing effect with PWM. - [How to create a PWM controller in VHDL](https://vhdlwhiz.com/pwm-controller/): Pulse-width modulation (PWM) is an efficient way of controlling the power to analog devices like motors or LEDs from purely digital FPGA pins using VHDL. - [How to make ModelSim from Quartus Prime Lite work on Ubuntu 20.04](https://vhdlwhiz.com/modelsim-quartus-prime-lite-ubuntu-20-04/): To make ModelSim from Intel Quartus Prime Lite work in Ubuntu 20.04, you have to make changes to the vsim script and compile 32-bit libraries it depends on. - [Using variables for registers or memory in VHDL](https://vhdlwhiz.com/variables-for-registers-or-memory/): Any VHDL variable that's read before it's written to becomes storage. That means registers (flip-flops) or memory. But is this a good design practice? - [Jenkins for FPGA projects using Vivado and GitHub on a Linux VPS](https://vhdlwhiz.com/jenkins-for-fpga/): This is a tutorial on setting up the Jenkins automation server for FPGA development. We install Xilinx Vivado on a Linux VPS and use GitHub for VHDL code. - [Should you use an FPGA or a microcontroller?](https://vhdlwhiz.com/fpga-or-microcontroller/): Many people use FPGAs when they could have gotten away with using microcontrollers. Let's talk about when it's appropriate to use an FPGA or an MCU. - [Dual 7-segment display FPGA controller](https://vhdlwhiz.com/dual-7-segment-display/): This is how to control a dual 7-segment display using VHDL. The two digits are stored as BCD and multiplexed to the correct digit on the 7-segment display. - [How to generate random numbers in VHDL](https://vhdlwhiz.com/random-numbers/): VHDL has a built-in pseudo-random generator. Use the uniform procedure as a basis to generate random real, integer, std_logic_vector, and time values. - [8 ways to create a shift register in VHDL](https://vhdlwhiz.com/shift-register/): These are the most efficient shift register implementations in VHDL for Xilinx, Intel, and Lattice. Download the code and understand the difference. - [An Introduction to FPGAs & Programmable Logic](https://vhdlwhiz.com/an-introduction-to-fpgas-programmable-logic/): Learn about FPGA and programmable logic in 45 minutes. What is an FPGA? Who uses FPGAs? How does an FPGA work? What are examples of products that use FPGAs? - [BMP file bitmap image read using TEXTIO](https://vhdlwhiz.com/read-bmp-file/): The easiest way to read an image file in VHDL is to convert it to a BMP file and read the bitmap raster graphics pixel data using the TEXTIO library. - [Stimulus file read in testbench using TEXTIO](https://vhdlwhiz.com/stimulus-file/): Test patterns for the DUT can be specified in a stimulus file. The testbench reads the text file and applies the signal values at the specified time values. - [How to initialize RAM from file using TEXTIO](https://vhdlwhiz.com/initialize-ram-from-file/): Reading binary, octal or hexadecimal literals from an ASCII file is a convenient way to give initial values to block RAM or ROM in VHDL. - [How to make an AXI FIFO in block RAM using the ready/valid handshake](https://vhdlwhiz.com/axi-fifo/): The AXI interface has built-in flow control without using additional control signals. Find out why the ready/valid handshake is ingenious. - [How to check if a vector is all zeros or ones](https://vhdlwhiz.com/how-to-check-if-a-vector-is-all-zeros-or-ones/): These are the best ways to check if a std_logic_vector contains all zeros or all ones. This function can check if a vector contains any value exclusively. - [FPGA course - Everything you need to know about the Dot Matrix VHDL Course](https://vhdlwhiz.com/fpga-course-everything-you-need-to-know/): The VHDL and FPGA course takes you from beginner or intermediate level to being able to understand and use advanced VHDL coding constructs for FPGA design. - [Constrained random verification](https://vhdlwhiz.com/constrained-random-verification/): Constrained random verification is a VHDL testbench strategy that relies on random interactions with the DUT while collecting functional coverage data. - [How to create a ring buffer FIFO in VHDL](https://vhdlwhiz.com/ring-buffer-fifo/): An advantage of the ring buffer FIFO is that it can be implemented in block RAM in the FPGA. This is the VHDL code for a generic ring buffer FIFO. - [What it's like working as an FPGA engineer in the defense industry](https://vhdlwhiz.com/working-in-the-defense-industry/): The defense industry employs a lot of FPGA engineers. Let me shed some light on how it is to work as an FPGA engineer for a defense contractor. - [Why you need to learn Tcl](https://vhdlwhiz.com/why-you-need-to-learn-tcl/): Tcl is the programming language that goes hand in hand with VHDL. Most FPGA and VHDL tools use Tcl as their console scripting language. - [Interactive testbench using Tcl](https://vhdlwhiz.com/interactive-testbench-using-tcl/): An interactive testbench is a simulator setup where input to the device under test (DUT) is provided by an operator while the testbench is running. - [How to create a self-checking testbench](https://vhdlwhiz.com/how-to-create-a-self-checking-testbench/): A self-checking testbench is a VHDL program that verifies the correctness of the device under test (DUT) without relying on... - [Why you always need a testbench](https://vhdlwhiz.com/why-you-always-need-a-testbench/): Testbenches are not optional in VHDL. You can only create what you can test. If you are unable to test a complex module, then it won’t work. I guarantee it. - [What's new in VHDL-2019](https://vhdlwhiz.com/vhdl-2019/): The next revision of VHDL is set to be released in 2019. The updated IEEE 1076 standard includes a number of improvements and changes to the VHDL language. - [How to create a linked list in VHDL](https://vhdlwhiz.com/linked-list/): Create a linked list in VHDL by using the Access Type and Protected Type. By implementing it in a package, it can by imported into another VHDL file. - [std_logic vs std_ulogic](https://vhdlwhiz.com/std_logic-vs-std_ulogic/): The std_logic is the most commonly used type in VHDL. It's a resolved type while the std_ulogic is the unresolved version of it. - [Delta cycles explained](https://vhdlwhiz.com/delta-cycles-explained/): Delta cycles are zero-time timesteps used by VHDL simulators. Master the delta cycle and you will for sure become a better VHDL engineer. - [One-process vs two-process vs three-process state machine](https://vhdlwhiz.com/n-process-state-machine/): Learn what the difference between a one-process state machine, a two-process state machine, and a three-process state machine is. - [How to use a procedure in a process in VHDL](https://vhdlwhiz.com/procedure-in-process/): A VHDL procedure declared within a process can read or drive any signals within its scope. Simplify your VHDL code by using a procedure in a process. - [How to use an impure function in VHDL](https://vhdlwhiz.com/impure-function/): An impure function in VHDL can read or write any signal within its scope, also those that are not on the parameter list. It is said to have side effects. - [How to use a function in VHDL](https://vhdlwhiz.com/function/): A function in VHDL is a type of subprogram that takes input parameters and always returns a value. There are two types of functions; pure and impure. - [How to create a finite-state machine in VHDL](https://vhdlwhiz.com/finite-state-machine/): Learn how to implement a finite-state machine (FSM) in VHDL. One of the most important things to master as a VHDL designer are state machines. - [How to use a procedure in VHDL](https://vhdlwhiz.com/using-procedure/): The procedure is a type of subprogram in VHDL which can operate on signals, variables, and constants. Procedures don't have return values, but parameters can be declared as outputs. In this tutorial you will learn how to simplify logic by using a procedure to avoid repetitive code in a process. - [How to create a timer in VHDL](https://vhdlwhiz.com/create-timer/): Learn how to create a real-time VHDL clock module. A VHDL timer is created by counting clock cycles, we use the clock period as a basis for measuring time. - [How to create a clocked process in VHDL](https://vhdlwhiz.com/clocked-process/): In a clocked process everything happens in sync with the clock signal. The flip-flop is the basic building block of synchronous logic design. - [How to use constants and Generic Map in VHDL](https://vhdlwhiz.com/constants-generic-map/): Learn how to use Constants and Generic Map to make your VHDL modules configurable. See how to convert an 8-bit multiplexer into a generic bit-width MUX. - [How to use Port Map instantiation in VHDL](https://vhdlwhiz.com/port-map/): The port map and port declaration defines a VHDL module's interface to the outside world. Use the port map for connecting the inputs and outputs. - [How to use a Case-When statement in VHDL](https://vhdlwhiz.com/case-when/): Case-When statements in VHDL cause the program to take one out of multiple different paths, depending on the value of a signal, variable, or expression. - [How to create a concurrent statement in VHDL](https://vhdlwhiz.com/concurrent-statement/): The concurrent statement is a signal assignment directly in the architecture region, outside of a process. Learn how they behave, and how to create them. - [How to use Signed and Unsigned in VHDL](https://vhdlwhiz.com/signed-unsigned/): The signed and unsigned types in VHDL are bit vectors which can be used in calculations. They overflow silently, and they get sign-extended by the compiler. - [How to create a signal vector in VHDL: std_logic_vector](https://vhdlwhiz.com/std_logic_vector/): The std_logic_vector type can be used for creating signal buses in VHDL. It is the array version of the std_logic, the most commonly used type in VHDL. - [How to use the most common VHDL type: std_logic](https://vhdlwhiz.com/std_logic/): The std_logic is the most common type used in VHDL. Think of this type as a single bit, the digital information carried by a single physical wire. - [How to create a process with a sensitivity list in VHDL](https://vhdlwhiz.com/sensitivity-list/): Learn how to use a sensitivity list to wake up a process in VHDL. Whenever any of the signals in the sensitivity list changes, the process will by executed. - [How to use conditional statements in VHDL: If-Then-Elsif-Else](https://vhdlwhiz.com/if-then-elsif-else/): Learn how to create branches in VHDL by using the If, Then, Elsif, and Else keywords. The expression will determine the path taken by the program. - [How to use Wait On and Wait Until in VHDL](https://vhdlwhiz.com/wait-on-wait-until/): Learn how to use the Wait On statement in VHDL to wake up a process, and how to wait until an expression is true by using the Wait Until statement. - [How a signal is different from a variable in VHDL](https://vhdlwhiz.com/signals-vs-variables/): Learn how a signal is different from a variable in VHDL. Our little experiment in the VHDL simulator shows the fundamental differences between the two. - [How to use a While loop in VHDL](https://vhdlwhiz.com/while-loop/): Learn how to use a While-Loop to iterate in VHDL. The While-Loop will continue to iterate as long as the expression it tests for evaluates to true. - [How to use a For loop in VHDL](https://vhdlwhiz.com/for-loop/): Learn how to create a For-Loop in VHDL. The For-loop is the best loop to use when you need to iterate over something a fixed number of times. - [How to use Loop and Exit in VHDL](https://vhdlwhiz.com/loop-and-exit/): Learn how to create a simple loop in VHDL using the Loop statement. Also, learn how to break out of any loop using the Exit statement. - [How to delay time in VHDL: Wait For](https://vhdlwhiz.com/wait-for/): Learn how to use the Wait For statement to delay time in VHDL. It can be used for pausing a VHDL program for a fixed amount of time in simulation . - [How to create your first VHDL program: Hello World!](https://vhdlwhiz.com/hello-world/): Learn how to print Hello World! with VHDL. This tutorial shows you how to create a bare minimum VHDL program, and how to run it in a VHDL simulator. - [How to install a VHDL simulator and editor for free](https://vhdlwhiz.com/free_vhdl_simulator_and_editor/): Guide for installing free VHDL tools. ModelSim Student Edition and Notepad++ are some of the most popular programs used by VHDL engineers. - [What is VHDL?](https://vhdlwhiz.com/what-is-vhdl/): What is VHDL? A computer language used for designing digital electronic circuits. Here I explain in short what that means, and what VHDL is used for. --- ## Quizzes - [Quizzes](https://vhdlwhiz.com/quiz/): Here's a fun collection of VHDL and FPGA quizzes. Assess your skill level and learn from the explanations after you submit an answer. - [Basic VHDL quiz](https://vhdlwhiz.com/basic-vhdl-quiz/): Quiz with 28 VHDL and FPGA design questions for beginners in random order, all with explanations for the correct answers. - [Basic VHDL quiz - Part 1](https://vhdlwhiz.com/basic-vhdl-quiz-part-1/): Test your VHDL skills with this multiple choice quiz! This quiz belongs to part 1 of the Basic VHDL Tutorials series for beginners. - [Basic VHDL quiz - Part 2](https://vhdlwhiz.com/basic-vhdl-quiz-part-2/): Test your coding skills with this VHDL quiz after completing tutorials 6-11 from the Basic VHDL Tutorial series! - [Basic VHDL quiz – Part 3](https://vhdlwhiz.com/basic-vhdl-quiz-part-3/): Test your progress with this VHDL quiz after completing tutorials 12-17 from the Basic VHDL Tutorial series! - [Basic VHDL quiz - Part 4](https://vhdlwhiz.com/basic-vhdl-quiz-part-4/): Test your progress with this VHDL quiz after completing part 4 of the Basic VHDL Tutorial series! --- ## VHDL and FPGA terminology - [VHDL and FPGA terminology](https://vhdlwhiz.com/terminology/): The terminology list for VHDL and FPGA related words and phrases contain definitions and descriptions for technical jargon. - [Behavioral model](https://vhdlwhiz.com/terminology/behavioral-model/): A behavioral model is a VHDL module that emulates another VHDL module or an external system in simulation. Behavioral models... - [Bitstream](https://vhdlwhiz.com/terminology/bitstream/): A bitstream is a file that contains the configuration information for an FPGA. It is also known as a bit... - [Block RAM](https://vhdlwhiz.com/terminology/block-ram/): Block RAM (BRAM) is a type of on-chip random-access memory (RAM) found on most FPGAs. Usually, the chip provides rows... - [Bus functional model (BFM)](https://vhdlwhiz.com/terminology/bus-functional-model/): A BFM is a behavioral model that replaces parts of your design or an external system, and its purpose is to mimic the missing subsystem. - [Clock domain crossing](https://vhdlwhiz.com/terminology/clock-domain-crossing/): Clock domain crossing (CDC) means facilitating data transfer from logic governed by one clock net in the FPGA to logic... - [Clock net](https://vhdlwhiz.com/terminology/clock-net/): A clock net or clock tree is a dedicated network of wiring and buffers optimized for routing a clock signal... - [Combinational logic](https://vhdlwhiz.com/terminology/combinational-logic/): An RTL module or process that isn’t triggered by a clock edge is said to be combinational. The outputs are... - [Composite type](https://vhdlwhiz.com/terminology/composite-type/): A composite type is a datatype consisting of several subelements. In VHDL, that can be either an array type or a record type. - [Constraints](https://vhdlwhiz.com/terminology/constraints/): A constraint is a rule that dictates a placement or timing restriction for the implementation. Constraints are not VHDL, and... - [Delta cycle](https://vhdlwhiz.com/terminology/delta-cycle/): Delta cycles are zero-time timesteps used by VHDL simulators for modeling chained events during code execution. The outputs from a... - [Driver](https://vhdlwhiz.com/terminology/driver/): A driver in VHDL is an instance or process that attempts to control the value of a signal. In the... - [Elaboration](https://vhdlwhiz.com/terminology/elaboration/): Elaboration is the first part of the synthesis step in the FPGA implementation design flow. During elaboration, the synthesis tool... - [Fan-out](https://vhdlwhiz.com/terminology/fan-out/): The fan-out for a primitive is the number of other logic elements connected to its output. When we say that... - [Hard core](https://vhdlwhiz.com/terminology/hard-core/): With the term “hard core” in FPGA design, we mean a component implemented in a dedicated physical circuit. It’s most... - [Hard macro](https://vhdlwhiz.com/terminology/hard-macro/): A hard macro is a prerouted netlist designed for a specific FPGA architecture. It is possible to place the macro... - [Infer](https://vhdlwhiz.com/terminology/infer/): The term “to infer” in FPGA design means intentionally describing a specific primitive with HDL code. The adept FPGA engineer... - [Latch](https://vhdlwhiz.com/terminology/latch/): A latch is a logic element that can sample and hold a binary value. But unlike a flip-flop, which is... - [Metastability](https://vhdlwhiz.com/terminology/metastability/): Metastability is an undesirable effect of setup and hold time violations in flip-flops where the output doesn’t settle quickly at... - [Multiplexer (MUX)](https://vhdlwhiz.com/terminology/multiplexer/): A multiplexer (MUX) is a basic digital logic element and a primitive found in FPGAs. The image below shows the... - [Multiplier (DSP)](https://vhdlwhiz.com/terminology/multiplier/): Multipliers are primitives in the FPGA capable of performing floating-point arithmetics. DSP block is an alternative name for a multiplier... - [Net](https://vhdlwhiz.com/terminology/net/): A net is a logical wire in a netlist. When designing VHDL, we often use multiple different signals when describing... - [Netlist](https://vhdlwhiz.com/terminology/netlist/): A netlist is a file format that describes the components, connectivity, and optionally, the placement and routing of an electronic... - [Primitive](https://vhdlwhiz.com/terminology/primitive/): Primitives are the smallest atomic logic element that we can configure on the FPGA. Ultimately, most of the FPGA fabric... - [Programming](https://vhdlwhiz.com/terminology/programming/): The term "programming" refers to the last step in the FPGA implementation flow where we program the FPGA with the configuration data. - [Register-transfer level (RTL)](https://vhdlwhiz.com/terminology/register-transfer-level/): When we say that a VHDL module is on the register-transfer level (RTL), we mean that it’s on the lowest... - [Sequential logic](https://vhdlwhiz.com/terminology/sequential-logic/): Sequential or clocked logic in VHDL is a process or component where the output changes on the clock signal’s active... - [Setup and hold time](https://vhdlwhiz.com/terminology/setup-and-hold-time/): Setup and hold time describes how long the input signal must be stable before and after the triggering clock edge.... - [Simulation](https://vhdlwhiz.com/terminology/simulation/): It’s difficult to debug VHDL code once it’s on the FPGA. The problem is that we have limited possibilities of... - [Single-event upset](https://vhdlwhiz.com/terminology/single-event-upset/): A single-event upset is when the natural background radiation causes an erroneous value in a digital logic element. It’s caused... - [Soft Core](https://vhdlwhiz.com/terminology/soft-core/): The term “soft core” refers to a component implemented using the configurable resources of the FPGA. It’s most commonly used... - [Synthesis](https://vhdlwhiz.com/terminology/synthesis/): Synthesis is the FPGA implementation design flow step that maps VHDL code to a technology-dependent netlist. The software responsible for... - [Testbench](https://vhdlwhiz.com/terminology/testbench/): A testbench is a VHDL module whose purpose is to let us simulate another module. All RTL modules depend on... - [Translate](https://vhdlwhiz.com/terminology/translate/): The term “translate” is ambiguous, even within the FPGA context. In the Xilinx design flow, “translate” refers to the process... - [Verification](https://vhdlwhiz.com/terminology/verification/): Verification means to generate proof that your application matches the specification. For example, we can verify a VHDL module by... --- ## VHDL attributes - [VHDL attributes](https://vhdlwhiz.com/attributes/): These are predefined attributes listed in the VHDL language reference manual. An attribute is a meta property attached to a type or object. - [Active](https://vhdlwhiz.com/attributes/active/): The active attribute works like a function call, returning true if s is active during the current simulation cycle and false if not. - [Ascending](https://vhdlwhiz.com/attributes/ascending/): The ascending attributes can be applied to scalar types or objects of them. It returns true if p has ascending range or false if not. - [Base](https://vhdlwhiz.com/attributes/base/): The base attribute returns the underlying type from which it originates. You get the root type that’s not a subtype. - [Converse](https://vhdlwhiz.com/attributes/converse/): When called on a mode view m, converse returns a derived view with the input modes transformed to outputs and vice versa. - [Delayed](https://vhdlwhiz.com/attributes/delayed/): When applied to a signal s, the delayed attribute produces a signal that’s a copy of s, but with the transitions delayed by t time units. - [Designated_subtype](https://vhdlwhiz.com/attributes/designated_subtype/): When called on an access type or file type, object p, the designated_subtype attribute returns the subtype that the object references. - [Driving](https://vhdlwhiz.com/attributes/driving/): The VHDL 'DRIVING attribute returns TRUE if the encapsulating process drives a value onto the signal, and it otherwise returns FALSE. - [Driving_value](https://vhdlwhiz.com/attributes/driving_value/): The driving_value VHDL attribute works like a function call, returning the value that the enclosing process drives onto the signal. - [Element](https://vhdlwhiz.com/attributes/element/): The element attribute returns the subtype of the array elements when applied to an array type, signal, or variable, as shown in the example. - [Event](https://vhdlwhiz.com/attributes/event/): Syntax s‘event When applied to a signal s, the event attribute works like a function call, returning true if an... - [High](https://vhdlwhiz.com/attributes/high/): The 'high attribute in VHDL returns the highest index value of the object regardless of ascending/descending range direction. - [Image](https://vhdlwhiz.com/attributes/image/): The VHDL 'image attribute acts as a function that converts an object's value to a string representation when applied to a type or subtype. - [Index](https://vhdlwhiz.com/attributes/index/): The 'index attribute returns the subtype of an array's index range for a given dimension in a VHDL array type, subtype, signal, or variable. - [Instance_name](https://vhdlwhiz.com/attributes/instance_name/): The VHDL instance_name attribute returns the full hierarchical path to a named entity, including signals, variables, constants, and labeled constructs. - [Left](https://vhdlwhiz.com/attributes/left/): The 'left attribute in VHDL returns the leftmost index from the type/object's definition regardless of ascending/descending range direction. - [Leftof](https://vhdlwhiz.com/attributes/leftof/): The 'leftof attribute returns the value to the left of X in a discrete scalar type’s range. VHDL-2019 has an additional shorthand notation. - [Length](https://vhdlwhiz.com/attributes/length/): The VHDL length attribute returns the number of elements in an array's index range, or (VHDL-2019) the number of values in a scalar subtype's range. - [Low](https://vhdlwhiz.com/attributes/low/): The 'low attribute in VHDL returns the lowest index value of the object regardless of ascending/descending range direction. - [Path_name](https://vhdlwhiz.com/attributes/path_name/): The VHDL path_name attribute returns a string with the hierarchical path to a named entity, similar but less detailed than instance_name. - [Pos](https://vhdlwhiz.com/attributes/pos/): The VHDL 'pos attribute is a function that returns the position number of a value in a discrete or physical type or subtype, as an integer. - [Quiet](https://vhdlwhiz.com/attributes/quiet/): The quiet attribute produces a derived signal of boolean type that is true if s was quiet for t time before the current simulation time. - [Range](https://vhdlwhiz.com/attributes/range/): The 'range attribute in VHDL returns the index range of a constrained array or, since VHDL‑2019, the range of a scalar type or subtype. - [Record](https://vhdlwhiz.com/attributes/record/): The VHDL 'record attribute returns the implicit record type that describes a scalar range's left bound, right bound, and direction. - [Reverse_range](https://vhdlwhiz.com/attributes/reverse_range/): The VHDL reverse_range attribute mirrors the range attribute, returning the same bounds but with to and downto directions swapped. - [Right](https://vhdlwhiz.com/attributes/right/): The 'right attribute in VHDL returns the rightmost index from the type/object's definition regardless of ascending/descending range direction. - [Rightof](https://vhdlwhiz.com/attributes/rightof/): The 'rightof attribute returns the value to the right of X in a discrete scalar type’s range. VHDL-2019 has an additional shorthand notation. - [Simple_name](https://vhdlwhiz.com/attributes/simple_name/): The VHDL simple_name attribute returns the name of a named entity as a lowercase string. It can be useful for refactoring-safe log messages. - [Stable](https://vhdlwhiz.com/attributes/stable/): The stable attribute produces a derived boolean signal that is false if there were events on s for t time before the current simulation time. - [Subtype](https://vhdlwhiz.com/attributes/subtype/): The VHDL 'subtype attribute returns the fully constrained subtype of an object, including any index constraints from its declaration. - [Val](https://vhdlwhiz.com/attributes/val/): The VHDL 'val attribute is a function that returns the value at a given integer position within a discrete or physical type or subtype. Inverse of 'pos. --- ## VHDL libraries and packages - [VHDL libraries and packages](https://vhdlwhiz.com/packages/): Reference for the VHDL libraries and packages defined by IEEE Std 1076-2019, including the IEEE library and the predefined packages it provides. - [STD library](https://vhdlwhiz.com/packages/std/): The STD library defined by IEEE 1076-2019: STANDARD predefined types, TEXTIO file I/O, ENV environment access, and REFLECTION introspection (VHDL 2019). - [ENV package declaration](https://vhdlwhiz.com/packages/std/env/) - [REFLECTION package declaration](https://vhdlwhiz.com/packages/std/reflection/): STD.REFLECTION: run-time reflection API exposing VHDL type and value metadata via mirror protected types. New in VHDL 2019. - [STANDARD package declaration](https://vhdlwhiz.com/packages/std/standard/) - [TEXTIO package declaration](https://vhdlwhiz.com/packages/std/textio/): STD.TEXTIO: text file I/O for VHDL. LINE pointers, the TEXT file type, and READ/WRITE/READLINE/WRITELINE for predefined scalar types. VHDL 2019. - [IEEE library](https://vhdlwhiz.com/packages/ieee/): The IEEE library defined by IEEE 1076-2019: STD_LOGIC_1164, NUMERIC arithmetic, MATH_REAL, MATH_COMPLEX, and the fixed and floating-point packages. - [FIXED_FLOAT_TYPES package declaration](https://vhdlwhiz.com/packages/ieee/fixed_float_types/): IEEE.FIXED_FLOAT_TYPES: rounding mode and overflow style enums consumed as generics by FIXED_GENERIC_PKG and FLOAT_GENERIC_PKG. VHDL 2019. - [FIXED_GENERIC_PKG package declaration](https://vhdlwhiz.com/packages/ieee/fixed_generic_pkg/): IEEE.FIXED_GENERIC_PKG: generic binary fixed-point arithmetic on ufixed and sfixed: operators, comparisons, resize, conversions, textio. VHDL 2019. - [FIXED_GENERIC_PKG package body](https://vhdlwhiz.com/packages/ieee/fixed_generic_pkg/body/): IEEE.FIXED_GENERIC_PKG package body: reference implementation of fixed-point arithmetic, comparison, resize, conversion, and textio. VHDL 2019. - [FIXED_PKG package declaration](https://vhdlwhiz.com/packages/ieee/fixed_pkg/): IEEE.FIXED_PKG: standard instantiation of FIXED_GENERIC_PKG with round-nearest, saturate-on-overflow, and 3 guard bits. VHDL 2019. - [FLOAT_GENERIC_PKG package declaration](https://vhdlwhiz.com/packages/ieee/float_generic_pkg/): IEEE.FLOAT_GENERIC_PKG: generic IEEE-754 floating-point arithmetic on UNRESOLVED_float with operators, conversions, comparisons, textio. VHDL 2019. - [FLOAT_GENERIC_PKG package body](https://vhdlwhiz.com/packages/ieee/float_generic_pkg/body/): IEEE.FLOAT_GENERIC_PKG package body: reference implementation of IEEE-754 floating-point arithmetic, comparisons, conversions, textio. VHDL 2019. - [FLOAT_PKG package declaration](https://vhdlwhiz.com/packages/ieee/float_pkg/): IEEE.FLOAT_PKG: standard instantiation of FLOAT_GENERIC_PKG at IEEE-754 single precision (8-bit exponent, 23-bit mantissa). VHDL 2019. - [MATH_COMPLEX package declaration](https://vhdlwhiz.com/packages/ieee/math_complex/): IEEE.MATH_COMPLEX: COMPLEX and COMPLEX_POLAR record types, constants, and overloaded arithmetic, trig, log, and hyperbolic functions. VHDL 2019. - [MATH_COMPLEX package body](https://vhdlwhiz.com/packages/ieee/math_complex/body/): IEEE.MATH_COMPLEX package body: reference implementation of complex arithmetic, conversions, and transcendental functions on MATH_REAL. VHDL 2019. - [MATH_REAL package declaration](https://vhdlwhiz.com/packages/ieee/math_real/): IEEE.MATH_REAL: real-valued constants (MATH_PI, MATH_E) and elementary functions (SQRT, EXP, LOG, SIN, COS, ATAN) for VHDL models. VHDL 2019. - [MATH_REAL package body](https://vhdlwhiz.com/packages/ieee/math_real/body/): IEEE.MATH_REAL package body: reference implementation of trigonometric, logarithmic, root, and exponential functions for VHDL models. VHDL 2019. - [NUMERIC_BIT package declaration](https://vhdlwhiz.com/packages/ieee/numeric_bit/): IEEE.NUMERIC_BIT: synthesizable arithmetic, comparison, shift, logical, and conversion operators for SIGNED and UNSIGNED built on BIT. VHDL 2019. - [NUMERIC_BIT package body](https://vhdlwhiz.com/packages/ieee/numeric_bit/body/): IEEE.NUMERIC_BIT package body: reference implementation of arithmetic, comparison, shift, logical, and conversion functions on BIT vectors. VHDL 2019. - [NUMERIC_BIT_UNSIGNED package declaration](https://vhdlwhiz.com/packages/ieee/numeric_bit_unsigned/): IEEE.NUMERIC_BIT_UNSIGNED: arithmetic, comparison, shift, and conversion operators that interpret BIT_VECTOR as unsigned binary integers. VHDL 2019. - [NUMERIC_BIT_UNSIGNED package body](https://vhdlwhiz.com/packages/ieee/numeric_bit_unsigned/body/): IEEE.NUMERIC_BIT_UNSIGNED package body: BIT_VECTOR operators that delegate to NUMERIC_BIT for unsigned arithmetic. VHDL 2019. - [NUMERIC_STD package declaration](https://vhdlwhiz.com/packages/ieee/numeric_std/): IEEE.NUMERIC_STD: synthesizable arithmetic, comparison, shift, logical, and conversion operators for SIGNED and UNSIGNED on STD_LOGIC. VHDL 2019. - [NUMERIC_STD package body](https://vhdlwhiz.com/packages/ieee/numeric_std/body/): IEEE.NUMERIC_STD package body: reference implementation of arithmetic, comparison, shift, logical, and conversion on STD_LOGIC vectors. VHDL 2019. - [NUMERIC_STD_UNSIGNED package declaration](https://vhdlwhiz.com/packages/ieee/numeric_std_unsigned/): IEEE.NUMERIC_STD_UNSIGNED: arithmetic, comparison, shift, and conversion operators that interpret STD_ULOGIC_VECTOR as unsigned integers. VHDL 2019. - [NUMERIC_STD_UNSIGNED package body](https://vhdlwhiz.com/packages/ieee/numeric_std_unsigned/body/): IEEE.NUMERIC_STD_UNSIGNED package body: STD_ULOGIC_VECTOR operators that delegate to NUMERIC_STD for unsigned arithmetic. VHDL 2019. - [STD_LOGIC_1164 package declaration](https://vhdlwhiz.com/packages/ieee/std_logic_1164/): IEEE.STD_LOGIC_1164: the nine-value logic system (STD_ULOGIC, STD_LOGIC), resolution function, logical and shift operators, edge detection. VHDL 2019. - [STD_LOGIC_1164 package body](https://vhdlwhiz.com/packages/ieee/std_logic_1164/body/): IEEE.STD_LOGIC_1164 package body: reference implementation of the resolution function, logical/shift operators, conversions, and textio. VHDL 2019. - [STD_LOGIC_TEXTIO package declaration](https://vhdlwhiz.com/packages/ieee/std_logic_textio/): IEEE.STD_LOGIC_TEXTIO: pre-2008 compatibility aliases forwarding to READ/WRITE/HREAD/HWRITE/OREAD/OWRITE in STD_LOGIC_1164. VHDL 2019. - [Apache License 2.0](https://vhdlwhiz.com/packages/apache-license-2-0/): Full text of the Apache License, Version 2.0, the open-source license covering the IEEE 1076 OSR VHDL packages used in this reference. --- ## VHDL code snippets - [VHDL snippet library](https://vhdlwhiz.com/snippets/): This page contains VHDL code examples that may be useful for the community. I will publish snippets that I use in explanations and demos. - [2FF synchronizer](https://vhdlwhiz.com/snippets/2ff-synchronizer/): This VHDL process synchronizes an external, asynchronous signal to the local clock domain by using the 2FF (two-flip-flop) method) - [Do-while loop](https://vhdlwhiz.com/snippets/do-while-loop/): Do-while loops don't exist in VHDL, but they are easy to emulate. This loop runs at least once and tests the condition after each iteration. - [Edge detector](https://vhdlwhiz.com/snippets/edge-detector/): This VHDL edge detector process sets one of two Boolean signals whenever there is a rising or falling edge on the incoming std_logic signal. - [Fork and join](https://vhdlwhiz.com/snippets/fork-and-join/): VHDL doesn’t have fork and join constructs like SystemVerilog because it doesn’t need it. But you can easily implement execution... - [Get even or odd bits from a std_logic_vector](https://vhdlwhiz.com/snippets/get-even-or-odd-bits-from-std_logic_vector/): This function will construct a new std_logic_vector of half length and return only the bits with even or odd indexes.... - [Get the current date and time](https://vhdlwhiz.com/snippets/get-the-current-date-and-time/): You can easily get the current date and time during simulation and synthesis by using the TIME_RECORD that’s new in... - [Loop over string characters](https://vhdlwhiz.com/snippets/loop-over-string-characters/): This example shows how to loop over a string in VHDL and print the individual characters using a For loop. It works... - [Required number of bits](https://vhdlwhiz.com/snippets/required-number-of-bits/): You can use the following VHDL formulas to calculate the number of bits needed to represent a number. Both methods... - [Vivado: Export and import a project using Tcl](https://vhdlwhiz.com/snippets/vivado-write_project_tcl/): The Xilinx Vivado . xpr project files are binary and not suitable for version control or sharing with other people.... - [Vivado: Set VHDL-2019 or VHDL-2008 for all .vhd files](https://vhdlwhiz.com/snippets/vivado-set-vhdl-2019-or-2008-for-all-vhd-files/): To tell Xilinx Vivado to compile a VHDL file using the newer VHDL-2019 or VHDL-2008 revisions in the GUI, you... - [Write to a file from multiple VHDL processes](https://vhdlwhiz.com/snippets/write-to-a-file-from-multiple-vhdl-processes/): This demo testbench shows how to write to an output file during simulation from several different processes, three in this... --- ## Products - [Course: VHDL text rendering with AI-assisted verification in VUnit](https://vhdlwhiz.com/product/course-vhdl-text-rendering-with-ai-assisted-verification-in-vunit/): Build a Pmod OLED text renderer in VHDL with UART, backspace, and scrolling. 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