Interactive testbench using Tcl

Interactive Testbench using Tcl

An interactive testbench is a simulator setup where input to the device under test (DUT) is provided by an operator while the testbench is running. Most often, this would mean you entering commands in the simulator console to provide the DUT with stimulus.

While you should always create a self-checking testbench, an interactive testbench can be a nice supplement. It’s easier to perform ad-hoc testing with an interactive testbench at hand, than it is to change the code of the self-checking testbench.

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How to create a self-checking testbench

How to create a self-checking testbench

A self-checking testbench is a VHDL program that verifies the correctness of the device under test (DUT) without relying on an operator to manually inspect the output. The self-checking testbench runs entirely on its own, and prints an “OK” or “Failed” message in the end.

Every VHDL module should have an associated self-checking testbench. It’s important to be able to verify that all modules have the intended behavior at any time. For example,

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Why you always need a testbench

Why you always need a testbench

As most hardware engineers, I started off my computer science career by learning a sequential programming language. The first language I learned at the University of Oslo was Java. While it’s not considered to be the most exciting language today, at the time, Java was at the pinnacle of its popularity.

The engineers who built Java were trying to solve a number of issues which earlier languages were lacking in one blow. Perhaps a wise decision to do a fresh start instead of continuing down the C path and creating C+++.

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What’s new in VHDL-2019

VHDL-2019

The VHDL Analysis and Standardization Group (VASG), has been working for quite some time on finishing the draft for the upcoming VHDL-2019 revision of the language. The ballot has been held, and a list of approved changes has emerged.

What’s left before this becomes the latest revision of the VHDL language is for the draft to be reviewed by the IEEE Standards Review Committee. With their approval, IEEE 1076-2019 will become the official standard.

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How to create a Linked List in VHDL

Create a linked list in VHDL

The linked list is a dynamic data structure. A linked list can be used when the total number of elements is not known in advance. It grows and shrinks in memory, relative to the number of items it contains.

Linked lists are most conveniently implemented using classes in an object-oriented programming language. VHDL has some object-oriented features which can be used for abstracting away the complexity of the implementation from the user.

In this article we are going to use access types,

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std_logic vs std_ulogic

std_logic vs std_ulogic

VHDL includes few built-in types, but offers a number of additional types through extension packages. Two of the most widely used types are the std_logic and std_ulogic. The difference between them is that the former is resolved, while the latter isn’t.

Before we go on to investigate what it means that a type is resolved, let’s first look at the traits that the two types share in common.

Bit and boolean are part of the standard package,

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Delta cycles explained

Delta cycles explained

Delta cycles are non time-consuming timesteps used by VHDL simulators for modelling events during execution of VHDL code. They are events that happen in zero simulation time after a preceding event.

VHDL is a parallel programming language, while computers and CPUs work in a sequential manner. When a normal programming language is run, the CPU executes one instruction after the other. While in VHDL, there can be multiple sequences of logic that react to each other in ways that are not compatible with the standard computer architecture.

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One-process vs two-process vs three-process state machine

One-process vs two-process vs three-process state machine

Most of us stick to a certain way of writing a state machine. Perhaps you type out the construct that you are most familiar with without giving much thought to the alternatives. Depending on the method that you were taught when learning VHDL, you may prefer one method to another.

Over the years, I have seen many different state machine designs. To appease my curiosity, I set out to investigate the most common ways to design finite-state machines (FSMs) in VHDL.

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How to use a Procedure in a Process in VHDL

How to use a Procedure in a Process in VHDL

It is possible to drive external signals from a procedure. As long as the signal is within the scope of the procedure, it can be accessed for reading or writing, even if it isn’t listed in the parameter list.

Procedures that are declared in the declarative region of the architecture, cannot drive any external signals. This is simply because there are no signals in its scope at compile time. A procedure declared within a process,

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