Circular buffers are popular constructs for creating queues in sequential programming languages, but they can also be implemented in hardware. In this article we will create a ring buffer in VHDL to implement a FIFO in block RAM.
There are many design decisions you will have to make when implementing a FIFO. What kind of interface do you need? Are you limited by resources? Should it be resilient to over-read and overwrite? Is latency acceptable?