“STD_LOGIC_1164 package declaration

The nine-value logic system used by virtually every synthesisable VHDL design.

Use clause
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Source
ieee/std_logic_1164.vhdl in the IEEE 1076 OSR, tag 1076-2019
Apache License 2.0, © 2019 IEEE P1076 WG Authors
Length
309 lines
VHDL revisions
Originally IEEE Std 1164-1993; merged into 1076-2008 and updated through 1076-2019
Body
View package body ›

Overview

STD_LOGIC_1164 defines the nine-value logic type STD_ULOGIC (and its resolved subtype STD_LOGIC), the unconstrained vector types STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR, the resolution function, overloaded logical and shift operators, conversions to and from BIT, edge detection, and string conversion procedures for textual I/O.

Almost every other IEEE package, and almost every real-world design, depends on this one. The arithmetic packages (NUMERIC_STD, NUMERIC_STD_UNSIGNED) build on top of STD_LOGIC_VECTOR; synthesisable RTL uses STD_LOGIC for almost every signal.

What's defined here

Types
STD_ULOGIC (the nine-value enum: 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), STD_ULOGIC_VECTOR, STD_LOGIC (resolved subtype), STD_LOGIC_VECTOR (resolved subtype), and the constrained subtypes X01, X01Z, UX01, UX01Z.
Operator groups
Logical (scalar) · Logical (vector) · Shift & rotate · Conversion · Strength strippers · Edge detection · String I/O
Key named functions
resolved, To_bit, To_bitvector, To_StdULogic, To_StdLogicVector, To_StdULogicVector, TO_01, To_X01, To_X01Z, To_UX01, rising_edge, falling_edge, Is_X, TO_OSTRING, TO_HSTRING, READ, WRITE, OREAD, HREAD

VHDL source listing

ieee/std_logic_1164.vhdl: declaration (309 lines) 69 groups
License: Apache License 2.0 Download
doc

File header Comment block (53 lines)

lines 1–53
-- -----------------------------------------------------------------
-- 
-- Copyright 2019 IEEE P1076 WG Authors
-- 
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
-- 
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
-- 
--     http://www.apache.org/licenses/LICENSE-2.0
-- 
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied.  See the License for the specific language governing
-- permissions and limitations under the License.
--
--   Title     :  Standard multivalue logic package
--             :  (STD_LOGIC_1164 package declaration)
--             :
--   Library   :  This package shall be compiled into a library
--             :  symbolically named IEEE.
--             :
--   Developers:  IEEE model standards group (PAR 1164),
--             :  Accellera VHDL-TC, and IEEE P1076 Working Group
--             :
--   Purpose   :  This packages defines a standard for designers
--             :  to use in describing the interconnection data types
--             :  used in vhdl modeling.
--             :
--   Limitation:  The logic system defined in this package may
--             :  be insufficient for modeling switched transistors,
--             :  since such a requirement is out of the scope of this
--             :  effort. Furthermore, mathematics, primitives,
--             :  timing standards, etc. are considered orthogonal
--             :  issues as it relates to this package and are therefore
--             :  beyond the scope of this effort.
--             :
--   Note      :  This package may be modified to include additional data
--             :  required by tools, but it must in no way change the
--             :  external interfaces or simulation behavior of the
--             :  description. It is permissible to add comments and/or
--             :  attributes to the package declarations, but not to change
--             :  or delete any original lines of the package declaration.
--             :  The package body may be changed only in accordance with
--             :  the terms of Clause 16 of this standard.
--             :
-- --------------------------------------------------------------------
-- $Revision: 1228 $
-- $Date: 2008-04-30 10:04:53 +0930 (Wed, 30 Apr 2008) $
-- --------------------------------------------------------------------

use STD.TEXTIO.all;

package std_logic_1164 is

Logic state system (unresolved)


  -------------------------------------------------------------------
  -- logic state system  (unresolved)
  -------------------------------------------------------------------
  type STD_ULOGIC is ( 'U',             -- Uninitialized
                       'X',             -- Forcing  Unknown
                       '0',             -- Forcing  0
                       '1',             -- Forcing  1
                       'Z',             -- High Impedance
                       'W',             -- Weak     Unknown
                       'L',             -- Weak     0
                       'H',             -- Weak     1
                       '-'              -- Don't care
                       );

Unconstrained array of STD_ULOGIC

  -------------------------------------------------------------------
  -- unconstrained array of std_ulogic for use with the resolution function
  -- and for use in declaring signal arrays of unresolved elements
  -------------------------------------------------------------------
  type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;

Resolution function


  -------------------------------------------------------------------
  -- resolution function
  -------------------------------------------------------------------
  function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;

Logic state system (resolved)



  -------------------------------------------------------------------
  -- logic state system  (resolved)
  -------------------------------------------------------------------
  subtype STD_LOGIC is resolved STD_ULOGIC;

Unconstrained array of resolved STD_LOGIC


  -------------------------------------------------------------------
  -- unconstrained array of resolved std_ulogic for use in declaring
  -- signal arrays of resolved elements
  -------------------------------------------------------------------
  subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;

Common subtypes


  -------------------------------------------------------------------
  -- common subtypes
  -------------------------------------------------------------------
  subtype X01 is resolved STD_ULOGIC range 'X' to '1';    -- ('X','0','1')
  subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z';   -- ('X','0','1','Z')
  subtype UX01 is resolved STD_ULOGIC range 'U' to '1';   -- ('U','X','0','1')
  subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z';  -- ('U','X','0','1','Z')

Overloaded logical operators


  -------------------------------------------------------------------
  -- overloaded logical operators
  -------------------------------------------------------------------
fn

"and"

lines 106–106
  function "and"  (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
fn

"nand"

lines 107–107
  function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
fn

"or"

lines 108–108
  function "or"   (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
fn

"nor"

lines 109–109
  function "nor"  (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
fn

"xor"

lines 110–110
  function "xor"  (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
fn

"xnor"

lines 111–111
  function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
fn

"not"

lines 112–113
  function "not"  (l : STD_ULOGIC) return UX01;

Vectorized overloaded logical operators

  -------------------------------------------------------------------
  -- vectorized overloaded logical operators
  -------------------------------------------------------------------
fn

"and"

lines 117–117
  function "and"  (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"nand"

lines 118–118
  function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"or"

lines 119–119
  function "or"   (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"nor"

lines 120–120
  function "nor"  (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"xor"

lines 121–121
  function "xor"  (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"xnor"

lines 122–122
  function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"not"

lines 123–124
  function "not"  (l    : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"and" 2 functions

lines 125–127
  function "and"  (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
  function "and"  (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"nand" 2 functions

lines 128–130
  function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
  function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"or" 2 functions

lines 131–133
  function "or"   (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
  function "or"   (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"nor" 2 functions

lines 134–136
  function "nor"  (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
  function "nor"  (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"xor" 2 functions

lines 137–139
  function "xor"  (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
  function "xor"  (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"xnor" 2 functions

lines 140–142
  function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
  function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
fn

"and"

lines 143–143
  function "and"  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"nand"

lines 144–144
  function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"or"

lines 145–145
  function "or"   (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"nor"

lines 146–146
  function "nor"  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"xor"

lines 147–147
  function "xor"  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"xnor"

lines 148–149
  function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;

Shift operators

  -------------------------------------------------------------------
  -- shift operators
  -------------------------------------------------------------------
fn

"sll"

lines 154–154
  function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
fn

"srl"

lines 155–155
  function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
fn

"rol"

lines 156–156
  function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
fn

"ror"

lines 157–158
  function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;

Conversion functions

  -------------------------------------------------------------------
  -- conversion functions
  -------------------------------------------------------------------
fn

To_bit

lines 162–162
  function To_bit       (s : STD_ULOGIC; xmap : BIT        := '0') return BIT;
fn

To_bitvector

lines 163–164
  function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
fn

To_StdULogic

lines 165–165
  function To_StdULogic       (b : BIT) return STD_ULOGIC;
fn

To_StdLogicVector 2 functions

lines 166–167
  function To_StdLogicVector  (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
  function To_StdLogicVector  (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
fn

To_StdULogicVector 2 functions

lines 168–170
  function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
  function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
al

To_Bit_Vector, To_BV 2 aliases

lines 171–175
  alias To_Bit_Vector is
    To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
  alias To_BV is
    To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
al

To_Std_Logic_Vector, To_SLV 2 aliases

lines 176–180
  alias To_Std_Logic_Vector is
    To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
  alias To_SLV is
    To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
al

To_Std_Logic_Vector, To_SLV 2 aliases

lines 181–185
  alias To_Std_Logic_Vector is
    To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
  alias To_SLV is
    To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
al

To_Std_ULogic_Vector, To_SULV 2 aliases

lines 186–190
  alias To_Std_ULogic_Vector is
    To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
  alias To_SULV is
    To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
al

To_Std_ULogic_Vector, To_SULV 2 aliases

lines 191–195
  alias To_Std_ULogic_Vector is
    To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
  alias To_SULV is
    To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];

Strength strippers and type convertors

  -------------------------------------------------------------------
  -- strength strippers and type convertors
  -------------------------------------------------------------------
fn

TO_01 4 functions

lines 200–208
  function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
    return STD_ULOGIC_VECTOR;
  function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
    return STD_ULOGIC;
  function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
    return STD_ULOGIC_VECTOR;
  function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
    return STD_ULOGIC;
fn

To_X01 4 functions

lines 209–213
  function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
  function To_X01 (s : STD_ULOGIC) return X01;
  function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
  function To_X01 (b : BIT) return X01;
fn

To_X01Z 4 functions

lines 214–218
  function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
  function To_X01Z (s : STD_ULOGIC) return X01Z;
  function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
  function To_X01Z (b : BIT) return X01Z;
fn

To_UX01 4 functions

lines 219–223
  function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
  function To_UX01 (s : STD_ULOGIC) return UX01;
  function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
  function To_UX01 (b : BIT) return UX01;
fn

"??"

lines 224–225
  function "??" (l : STD_ULOGIC) return BOOLEAN;

Edge detection

  -------------------------------------------------------------------
  -- edge detection
  -------------------------------------------------------------------
fn

rising_edge

lines 229–229
  function rising_edge  (signal s : STD_ULOGIC) return BOOLEAN;
fn

falling_edge

lines 230–231
  function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;

Object contains an unknown

  -------------------------------------------------------------------
  -- object contains an unknown
  -------------------------------------------------------------------
fn

Is_X 2 functions

lines 235–237
  function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
  function Is_X (s : STD_ULOGIC) return BOOLEAN;

Matching relational operators

  -------------------------------------------------------------------
  -- matching relational operators
  -------------------------------------------------------------------
fn

"?=" 2 functions predefined

lines 241–245
  -- the following operations are predefined

  --  function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
  --  function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"?/=" 2 functions predefined

lines 246–248
  --  function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
  --  function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
fn

"?<" predefined

lines 249–249
  --  function "?<" (l, r  : STD_ULOGIC) return STD_ULOGIC;
fn

"?<=" predefined

lines 250–250
  --  function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
fn

"?>" predefined

lines 251–251
  --  function "?>" (l, r  : STD_ULOGIC) return STD_ULOGIC;
fn

"?>=" predefined

lines 252–253
  --  function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;

String conversion and write operations

  -------------------------------------------------------------------
  -- string conversion and write operations
  -------------------------------------------------------------------
fn

TO_STRING 2 functions predefined

lines 257–263
  -- the following operations are predefined

  -- function TO_STRING (value : STD_ULOGIC) return STRING;
  -- function TO_STRING (value : STD_ULOGIC_VECTOR) return STRING;

  -- explicitly defined operations
al

TO_BSTRING, TO_BINARY_STRING 2 aliases

lines 264–265
  alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
  alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
fnal

TO_OSTRING, TO_OCTAL_STRING function and alias

lines 266–267
  function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
  alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
fnal

TO_HSTRING, TO_HEX_STRING function and alias

lines 268–270
  function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
  alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
pr

READ 4 procedures

lines 271–276
  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);

  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
pr

WRITE 2 procedures

lines 277–282
  procedure WRITE (L         : inout LINE; VALUE : in STD_ULOGIC;
                   JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);

  procedure WRITE (L         : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
                   JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
al

BREAD 2 aliases

lines 283–284
  alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
al

BINARY_READ 2 aliases

lines 285–287
  alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
pr

OREAD 2 procedures

lines 288–289
  procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
  procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
al

OCTAL_READ 2 aliases

lines 290–292
  alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
pr

HREAD 2 procedures

lines 293–294
  procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
  procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
al

HEX_READ 2 aliases

lines 295–297
  alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
al

BWRITE, BINARY_WRITE 2 aliases

lines 298–300
  alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
  alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
pral

OWRITE, OCTAL_WRITE procedure and alias

lines 301–304
  procedure OWRITE (L         : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
                    JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
  alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
pral

HWRITE, HEX_WRITE procedure and alias

lines 305–308
  procedure HWRITE (L         : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
                    JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
  alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];

end package std_logic_1164;
License: Apache License 2.0 Download