VHDL module: Wishbone crossbar interconnect
This VHDL module lets multiple Wishbone masters talk to multiple slaves simultaneously using a crossbar switch topology.
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VHDL modules: Sorting algorithm FPGA implementations
This demo project contains five VHDL implementations of two hardware-friendly sorting algorithms: (Odd-even) Brick sort and Selection sort.
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VHDL registers UART test interface generator
$39This tool generates a VHDL module and a Python script to read from or write to any number of custom FPGA registers using UART.
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VHDL package: Binary file reader/writer
$29These VHDL packages provide a user-friendly interface for binary file access in simulation to read or write bit vectors of any length.
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VHDL package: WAV audio file reader/writer
$29These VHDL packages read and write WAV audio files. They provide a user-friendly way to run VHDL simulations on audio processing modules.
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VHDL module: AXI-style UART
$15This project contains three general-purpose, AXI compatible, universal asynchronous receiver-transmitter (UART) modules.
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VHDL package: Generic list of protected type
$15This VHDL package can store any data type in dynamic memory. It mimics the behavior of Python’s list class and supports negative indexing.
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VHDL RC servo controller using PWM
$0This VHDL module controls the position of an RC servo like the TowerPro SG90 motor using pulse-width modulation (PWM).
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VHDL PWM generator
$0This VHDL module generates a pulse-width modulation (PWM) signal with generic counter length and run-time configurable frequency.
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VHDL sine wave generator using block RAM
$0This VHDL module reads pre-calculated values from block RAM in the FPGA to generate a smooth sine wave pattern on the output signal.
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VHDL dual 7-segment display controller
$0This VHDL module shows a decimal value from 0 to 99 on the Pmod SSD: Seven-segment Display from Digilent or similar dual 7-segment display.
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VHDL debouncer – single switch or multiple bits
$0This VHDL project contains three modules that can debounce a switch or a button or arrays of them using a generate statement.
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