These downloadable projects from the VHDLwhiz shop are modules or packages implemented using VHDL.
Showing 1–12 of 13 results
This tool generates a VHDL module and a Python script to read from or write to any number of custom FPGA registers using UART.
These VHDL packages provide a user-friendly interface for binary file access in simulation to read or write bit vectors of any length.
These VHDL packages read and write WAV audio files. They provide a user-friendly way to run VHDL simulations on audio processing modules.
This project contains three general-purpose, AXI compatible, universal asynchronous receiver-transmitter (UART) modules.
This VHDL package can store any data type in dynamic memory. It mimics the behavior of Python’s list class and supports negative indexing.
This VHDL module controls the position of an RC servo like the TowerPro SG90 motor using pulse-width modulation (PWM).
This VHDL module generates a pulse-width modulation (PWM) signal with generic counter length and run-time configurable frequency.
This VHDL module reads pre-calculated values from block RAM in the FPGA to generate a smooth sine wave pattern on the output signal.
This VHDL module shows a decimal value from 0 to 99 on the Pmod SSD: Seven-segment Display from Digilent or similar dual 7-segment display.
This VHDL project contains three modules that can debounce a switch or a button or arrays of them using a generate statement.
This VHDL package contains an object-oriented linked list of protected type that implements a dynamic length FIFO for use in testbenches.
This VHDL implementation of a ring buffer FIFO has generic data width and depth settings.
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