This design consists of three debouncer modules, where two of them have identical entities. The first is a simple switch debouncer, while the other two are capable of debouncing an n-bit vector of switches.
The first n-bit debouncer uses a process within a generate statement to duplicate the logic. The other instantiates the one-bit debouncer within a generate statement to achieve the same result.
The modules are customizable for any clock speeds or number of switches through the
entity debouncer is generic ( timeout_cycles : positive ); port ( clk : in std_logic; rst : in std_logic; switch : in std_logic; switch_debounced : out std_logic ); end debouncer;
entity debouncer_n_bit is generic ( switch_count : positive; timeout_cycles : positive ); port ( clk : in std_logic; rst : in std_logic; switches : in std_logic_vector(switch_count - 1 downto 0); switches_debounced : out std_logic_vector(switch_count - 1 downto 0) ); end debouncer_n_bit ;
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Generate statement debouncer example
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