The Basic VHDL tutorial series covers the most important features of the VHDL language. This VHDL course for beginners will help you understand the fundamental principles of the language. It is a primer for you to be able to excel at VHDL.
If you are unsure of what VHDL is, start here: What is VHDL?
How to get started
No hardware is required, meaning you can start right away! The VHDL tutorial exercises are run only in a VHDL simulator. The ModelSim VHDL simulator is used in this series, but you can use any VHDL simulator that you have access to.
As a student, you can install the student edition of ModelSim for free. ModelSim is the most common VHDL simulator, and therefore the one you are most likely to encounter in your first job. Being familiar with the industry standard of simulators is advantageous. You can put that on your resume to make it more relevant.
Download the course material by clicking the banner below. You will receive a zip file containing a folder with all the exercises, and a folder with all the answers. I recommend that you use the .vhd files in the exercise folder as a starting point for each of the tutorials. This will save you from repeating the same code over and over again.
For each tutorial, open the corresponding .vhd file from the exercises folder. You only need to replace the TODO comments with your code to complete each exercise. You are only allowed to peek at the .vhd file from the answers folder if you run into problems 🙂
Each of the tutorials cover one basic concept. Start by clicking the first banner to get your development environment up and running. Try out the exercises on your own computer.
Start with number 1 and work your way down to number 23, which is the final one. After each section, you can take the VHDL quiz to test your skills as you progress.
Click the images to get started!
In part 1 of the VHDL tutorial series you will become familiar with the tools of the trade. If you haven’t done so already, you will begin by installing the VHDL simulator and code editor.
You will write and run your first VHDL program in the very first tutorial. You will learn the core features of the VHDL language, such as printing text to the console, and three different loop statements.
We will explore some peculiarities that arise due to the fact that VHDL is a parallel programming language made for creating digital logic. You will learn how to operate the most important tool that the digital logic engineer has, namely the VHDL simulator.
Install a VHDL simulator and editor for free
Your first VHDL program:
How to delay time in VHDL:
How to use Loop and Exit in VHDL
How to use a For-Loop in VHDL
How to use a While-Loop in VHDL
Now that you are starting to get familiar with the VHDL language, it is time to dive deeper into some of the concepts that are unique to hardware description languages.
You will learn how a bit, the value which can be carried by a single wire, can be represented in VHDL. You will also see that while VHDL has variables, like any other programming language, signals are actually the preferred storage unit in digital design.
After this section, you will know the difference between a signal and a variable. You will also have touched on the subject of inter-process communication by using signals and sensitivity lists.
How a signal is different from a variable in VHDL
How to use Wait On and Wait Until in VHDL
How to use conditional statements in VHDL:
How to create a process with a Sensitivity List in VHDL
How to use the most common VHDL type:
How to create a signal vector in VHDL:
In part 3 you will learn how integer numbers are represented in VHDL. You will see how the fine-grained control we have over bits in VHDL can be used to your advantage. We will explore some of the pitfalls of working with numbers at the bit-level.
You will learn how to create a module in VHDL. You will also learn about some basic building blocks of digital design; the multiplexer and the flip-flop.
After this section, you will know the difference between a concurrent process and a clocked process in VHDL.
How to use Signed and Unsigned in VHDL
How to create a Concurrent Statement in VHDL
How to use a Case-When statement in VHDL
How to use Port Map instantiation in VHDL
How to use Constants and Generic Map in VHDL
How to create a Clocked Process in VHDL
In the last section in this VHDL course, we will start by creating a fully functional timekeeping module in VHDL. You will learn the difference between simulation time and real-time in VHDL.
You will use what you have learned to solve a real-life problem. We will create a traffic lights control system for managing a road intersection. While doing so, you will learn about the one of the most important concepts in digital design, the finite-state machine.
Finally, you will learn to factor out repetitive code into subprograms like functions and procedures. Divide and conquer is the only viable strategy for surviving as a VHDL engineer in the long run.
How to create a Timer in VHDL
How to use a Procedure in VHDL
How to create a
How to use a Function in VHDL
How to use an
How to use a Procedure in a Process in VHDL
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