I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
Similar Posts
How to use Signed and Unsigned in VHDL
The signed and unsigned types in VHDL are bit vectors, just like the std_logic_vector type. The difference is that while the std_logic_vector is great for implementing data buses, it’s useless for performing arithmetic operations. If you try to add any number to a std_logic_vector type, ModelSim will produce the compilation error: No feasible entries for…
How to use the most common VHDL type: std_logic
The most common type used in VHDL is the std_logic. Think of this type as a single bit, the digital information carried by a single physical wire. The std_logic gives us a more fine-grained control over the resources in our design than the integer type, which we have been using in the previous tutorials. Normally,…
Should I learn VHDL if Verilog is becoming more popular?
Which HDL is the most popular, and should I learn VHDL or Verilog? That’s a question I often get asked, and it’s understandable. People want to future-proof their learning by betting on the winning horse. But which one is it, and does it matter?
How to stop simulation in a VHDL testbench
How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run. The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving…
How to use a For loop in VHDL
In the previous tutorial we learned to create an infinite loop by using the loop statement. We also learned how the break out of a loop by using the exit statement. But what if we want the loop to iterate a certain number of times? The For-Loop is the easiest way to accomplish this. The…
How to use constants and Generic Map in VHDL
Creating modules is a great way to reuse code, but often you need the same module with smaller variations throughout your design. This is what generics and the generic map are for. It allows you to make certain parts of the module configurable at compile-time. Constants are used when we want to avoid typing the…


First of all, thank you so very much!
These are by far the most comprehensible tutorials I have come across like ever!
Brilliant work.
So here my two cents out of gratitude:
Basic VHDL Quiz – part 4
Which statement is not true?
Answer 3 : The return statement cannot be omitted.
-> Correct
So the return statement CAN be omitted???
“Unlike in most other programming languages, the return keyword is mandatory in functions in VHDL.”
Confused by double negation. Me or you 😉
Good catch! I’ve changed the answer now. I was trying to make you think, but in the process I confused myself too 🙂
“The return-keyword cannot be used in a procedure”. I believe that this is incorrect, e.g.
https://web.archive.org/web/20200629023040/http://vhdl.renerta.com:80/source/vhd00060.htm
It is true, of course, that you cannot return a value with it, that’s the only (?) difference between procedures and functions. But, as in other languages, you can use “return” as control flow statement to “force an exit”.
You are right! I missed the possibility of using return statements in procedures without returning a value. According to the Renata link you posted, functions must return a value, while procedures can have return statements, but then without a return value.
I am changing this question.