VHDL attributes


These are predefined attributes listed in the VHDL language reference manual.

An attribute in VHDL is a meta property that’s attached to a type or object. We can use them to get information about the item that goes beyond the value it carries. Some attributes are only for simulation, while others are also useful for avoiding hard-coded constants in synthesizable code.

Note: This list is still incomplete. I’m adding sections regularly and will remove this notice when finished.


Active

Syntax
s'active

When applied to a signal s, the active attribute works like a function call, returning true if s is active during the current simulation cycle and false if not.

If s is a composite signal, the whole signal is considered active if one of the subelements are.

The term active means that a signal assignment, force, or release is scheduled for the current simulation cycle, even if it’s the same value as the signal already had.

Example
    signal s : std_logic := '0';

begin

    process
    begin
        s <= '0';
        wait;
    end process;

    process
    begin
        report "Active: " & boolean'image(s'active);
        wait for 0 ns;
        report "Active: " & boolean'image(s'active);
        wait for 0 ns;
        report "Active: " & boolean'image(s'active);
        wait;
    end process;
# ** Note: Active: false
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: Active: true
#    Time: 0 ns  Iteration: 1  Instance: /test_tb
# ** Note: Active: false
#    Time: 0 ns  Iteration: 2  Instance: /test_tb

Ascending

Syntax
p'ascending
a'ascending[(n)]

The ascending attributes can be applied to scalar types or objects of them, including subtypes and aliases. It returns a boolean value that will be true if p has ascending range or false if it’s descending.

When called on an array a, the optional n parameter specifies which index range to check. It defaults to 1 when omitted, which is the only legal value for one-dimensional arrays anyway. But for multi-dimensional arrays, an n > 1 will check the direction of a subdimension.

Example
    signal s : std_logic_vector(7 downto 0);
    type t1 is array (0 to 9) of bit;
    type t2 is array (0 to 9, 7 downto 0) of bit;

begin

    process
    begin
        report "s'ascending: " & boolean'image(s'ascending);
        report "t1'ascending: " & boolean'image(t1'ascending);
        report "t2'ascending: " & boolean'image(t2'ascending);
        report "t2'ascending(1): " & boolean'image(t2'ascending(1));
        report "t2'ascending(2): " & boolean'image(t2'ascending(2));
        report "integer'ascending: " & boolean'image(integer'ascending);
        report "std_logic'ascending: " & boolean'image(std_logic'ascending);
        wait;
    end process;
# ** Note: s'ascending: false
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: t1'ascending: true
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: t2'ascending: true
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: t2'ascending(1): true
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: t2'ascending(2): false
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: integer'ascending: true
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: std_logic'ascending: true
#    Time: 0 ns  Iteration: 0  Instance: /test_tb

Base

Syntax
p'base≥ VHDL-2019
t'base

When applied to an object, type, or subtype p, the base attribute returns the underlying type from which it originates. If there are multiple layers of subtypes, you get the root type that’s not a subtype.

You cannot use this attribute standalone. It must appear in conjunction with a second attribute, for example, p'base'right.

Language revisions before VHDL-2019 only support calling 'base on types and subtypes (t).

Example
    subtype hex_type is integer range 0 to 15;
    subtype dec_type is hex_type range 0 to 9;
    signal p : dec_type;

begin

    process
    begin
        report "hex_type'base'right: " & integer'image(hex_type'base'right);
        report "dec_type'base'right: " & integer'image(dec_type'base'right);
        report "p'subtype'base'right: " & integer'image(p'subtype'base'right);
        -- (In VHDL-2019, you can do: p'base'right)
        wait;
    end process;
# ** Note: hex_type'base'right: 2147483647
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: dec_type'base'right: 2147483647
#    Time: 0 ns  Iteration: 0  Instance: /test_tb
# ** Note: p'subtype'base'right: 2147483647
#    Time: 0 ns  Iteration: 0  Instance: /test_tb

Converse

Syntax
m'converse≥ VHDL-2019

VHDL-2019 adds mode views to interfaces and the converse attribute attribute along with them. When called on a mode view m, converse returns a derived view with the modes from m transformed as follows:

in out
out in
inout inout
buffer in
mode view (m) m'converse

Example

Consider this record and corresponding mode view:

type spi_if is record
  sclk : std_logic;
  mosi : std_logic;
  miso : std_logic;
end record;

view spi_master_if of spi_if is
  sclk : out;
  mosi : out;
  miso : in;
end view spi_master_if;

We could create an identical view with reversed data directions like this:

view spi_slave_if of spi_if is
  sclk : in;
  mosi : in;
  miso : out;
end view spi_slave_if;

Or we can achieve the same by using the converse attribute:

view spi_slave_if is spi_master_if'converse;

Quiet

Syntax
s'quiet[(t)]

When applied to a signal s, the quiet attribute produces a derived signal of boolean type. The resulting signal’s value is true if s was quiet for t time before the current simulation time. Otherwise, it has the value false.

The time value defaults to 0 ns if you omit the optional t parameter.

A signal is quiet if no assignments happen within the given period. When a value is scheduled or forced onto the signal, it is no longer quiet, even if it’s the same value as the signal already had.

Example
  signal quiet_50_ns : boolean;

begin

  quiet_50_ns <= sig'quiet(50 ns);

Stable

Syntax
s'stable[(t)]

When applied to a signal s, the stable attribute produces a derived signal of boolean type. The resulting signal’s value is false if there were events on s for t time before the current simulation time. If there were no events, it is true.

The time value defaults to 0 ns if you omit the optional t parameter.

An event is when a signal’s value changes. Assigning the same value that the signal already has doesn’t trigger events.

Example 1
  signal stable_50_ns : boolean;

begin

  stable_50_ns <= sig'stable(50 ns);
Example 2
process
begin
  wait until falling_edge(sclk);
 
  assert cs'stable(10 ns)
    report "Falling SCLK too close to falling Chip Select"
    severity failure;
   
end process;