## Part 5: Polyphase FIR filters

Polyphase filters are a class of specialized filters used in sample rate conversion. Whereas most FIR filters have one delay line, Polyphase filters have multiple. To understand the logic behind this, we’ll first have to dive into the topic of sample rate conversion.

## Part 4: FIR filter testing

So far, the spotlight has fallen over the FIR filter design and its various forms. However, there is a problem that is just as important – how to ensure the implementation is working correctly. Whereas there are some standard techniques, it’s not always clear whether the design is error-proof. Therefore, this post discusses the most essential testing procedures and introduces a verification method that can easily incorporate them.

## Should I learn VHDL if Verilog is becoming more popular?

Which HDL is the most popular, and should I learn VHDL or Verilog? That’s a question I often get asked, and it’s understandable. People want to future-proof their learning by betting on the winning horse. But which one is it, and does it matter?

## Function and procedure call overhead in VHDL

There are controversies in the VHDL community about how you can and shouldn’t use subprograms. Some say you should avoid using functions or procedures in synthesizable (RTL) code. While there are debatable subjective reasons to restrict the use of subprograms, many of these beliefs stem from myths or misconceptions. Therefore, I’m writing this article to…

## How the AXI-style ready/valid handshake works

The ready/valid hardware data transfer protocol is simple and ingenious, providing flow control with only two control signals. The rules are straightforward: data transfer only happens when both ready and valid are ‘1’ during the same clock cycle.

## Short-circuit operations in VHDL

A binary operator is an operator that takes exactly two arguments. Examples of such are addition or multiplication and, of course, the familiar Boolean logical operators we use in VHDL: and, or nand nor xor and xnor.

## Operator precedence in VHDL

VHDL groups operators into classes with different precedence levels. Operators are evaluated according to their classes, starting with the highest level. Operators of the same class don’t have any predefined priority. Instead, they are evaluated left to right in the order they appear in the code.

## How to define and print multiline string literals in VHDL

This article shows how to work with strings containing line breaks in VHDL. Read on to learn how to split long lines in your VHDL code, print text containing newline characters, and how VHDL differs from regular programming languages regarding non-printing control characters in strings.

## Part 3: FIR filter types

The previously discussed filter describes a general-purpose device that can fit in many applications but is not necessarily the optimal solution. This is where application-specific FIR structures come in. Therefore, this post aims to present some of the more popular filter structures used in specialized applications.

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