Basic VHDL quiz - All questions

Basic VHDL - All questions

Have fun and learn from this VHDL and FPGA design quiz with 28 questions for beginners and intermediate learners in random order.

All questions include an explanation for the correct answer that will be shown after you make your selection.

You should be able to answer most of them after taking VHDLwhiz's free Basic VHDL Tutorials course.

1 / 28

What will this code print out?

2 / 28

What will this code print out?

3 / 28

Which is equivalent to this concurrent process?

4 / 28

What will this code print out?

5 / 28

What value will Output have after running this code?

6 / 28

How do we measure real-time in an FPGA by using VHDL?

7 / 28

What is the value of the Slv signal?

8 / 28

Is the use of exit; in this process legal?

9 / 28

What is true regarding the := 0 in this procedure declaration?

10 / 28

How many times will this process print "Haha!"?

11 / 28

What is wrong with this process?

12 / 28

What does "setup time" for a flip-flop mean?

13 / 28

Where can a regular variable be declared in this code?

14 / 28

Which statement is correct regarding these snippets?

15 / 28

How much simulation time does the For loop take?

16 / 28

Which statement is true

17 / 28

Which statement describes a fundamental flaw in this fire control system?

18 / 28

Which statement is true about the signed type?

19 / 28

How are impure functions different from pure functions?

20 / 28

Which process is equivalent to this one?

21 / 28

What is the value of the Slv signal?

22 / 28

Which statement about functions is true?

23 / 28

Why do we normally not think about setup and hold time when designing in VHDL?

24 / 28

What will this code print out?

25 / 28

Which is true about the port declaration?

26 / 28

How will values that are passed through the generic map appear in the module?

27 / 28

What will this code print out?

28 / 28

How many times will the value of i be printed?

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