I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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![How to create a concurrent statement in VHDL](https://vhdlwhiz.com/wp-content/uploads/2017/07/concurrent_statement.png)
How to create a concurrent statement in VHDL
A concurrent statement in VHDL is a signal assignment within the architecture, but outside of a normal process construct. The concurrent statement is also referred to as a concurrent assignment or concurrent process. When you create a concurrent statement, you are actually creating a process with certain, clearly defined characteristics. Concurrent statements are always equivalent…
![How to use Wait On and Wait Until in VHDL](https://vhdlwhiz.com/wp-content/uploads/2017/07/wait_on_wait_until.png)
How to use Wait On and Wait Until in VHDL
In the previous tutorial we learned the main differences between signals and variables. We learned that signals have a broader scope than variables, which are only accessible within one process. So how can we use signals for communication between several processes? We have already learned to use wait; to wait infinitely, and wait for to…
![Basic VHDL quiz – Part 4](https://vhdlwhiz.com/wp-content/uploads/2018/10/quiz-part-4.jpg)
Basic VHDL quiz – Part 4
Test your progress with this VHDL quiz after completing part 4 of the Basic VHDL Tutorial series!
Constrained random verification
Constrained random verification is a testbench strategy that relies on generating pseudo-random transactions for the device under test (DUT). The goal is to reach functional coverage of a number of predefined events through random interaction with the DUT. Open Source VHDL Verification Methodology (OSVVM) is a free VHDL library which includes a number of convenient…
![How to use Port Map instantiation in VHDL](https://vhdlwhiz.com/wp-content/uploads/2017/09/port_map.png)
How to use Port Map instantiation in VHDL
A module is a self-contained unit of VHDL code. Modules communicate with the outside world through the entity. Port map is the part of the module instantiation where you declare which local signals the module’s inputs and outputs shall be connected to. In previous tutorials in this series we have been writing all our code…
![FPGA course – Everything you need to know about the Dot Matrix VHDL Course](https://vhdlwhiz.com/wp-content/uploads/2019/07/dot-matrix-featured-768x432.jpg)
FPGA course – Everything you need to know about the Dot Matrix VHDL Course
I’m excited to announce that the VHDL and FPGA course that I have been working on for the last six months is starting to become complete. The course is in beta at the moment, and I am planning on launching it for the first time this autumn. Who is the FPGA course for? The FPGA…