Basic VHDL quiz - All questions

Basic VHDL - All questions

Have fun and learn from this VHDL and FPGA design quiz with 28 questions for beginners and intermediate learners in random order.

All questions include an explanation for the correct answer that will be shown after you make your selection.

You should be able to answer most of them after taking VHDLwhiz's free Basic VHDL Tutorials course.

1 / 28

How much simulation time does the For loop take?

2 / 28

Which is equivalent to this concurrent process?

3 / 28

What will this code print out?

4 / 28

Which statement describes a fundamental flaw in this fire control system?

5 / 28

Why do we normally not think about setup and hold time when designing in VHDL?

6 / 28

How many times will the value of i be printed?

7 / 28

Is the use of exit; in this process legal?

8 / 28

Which statement about functions is true?

9 / 28

What will this code print out?

10 / 28

What does "setup time" for a flip-flop mean?

11 / 28

What is wrong with this process?

12 / 28

Which statement is true about the signed type?

13 / 28

What will this code print out?

14 / 28

What will this code print out?

15 / 28

Which statement is correct regarding these snippets?

16 / 28

How will values that are passed through the generic map appear in the module?

17 / 28

What is true regarding the := 0 in this procedure declaration?

18 / 28

Where can a regular variable be declared in this code?

19 / 28

What is the value of the Slv signal?

20 / 28

How many times will this process print "Haha!"?

21 / 28

Which process is equivalent to this one?

22 / 28

What value will Output have after running this code?

23 / 28

What will this code print out?

24 / 28

Which is true about the port declaration?

25 / 28

What is the value of the Slv signal?

26 / 28

How do we measure real-time in an FPGA by using VHDL?

27 / 28

Which statement is true

28 / 28

How are impure functions different from pure functions?

Your score is

0%

Similar Posts

Leave a Reply

Your email address will not be published. Required fields are marked *