Tcl is the programming language that goes hand in hand with VHDL. You may choose to learn Verilog instead of VHDL, but you will be exposed to Tcl no matter which HDL you decide to use. That is because most FPGA related programs, such as simulators and synthesis tools, use Tcl in their command shells.
Having a standardized scripting language for software tools is actually very clever. It enables you to transfer your scripting skills from one tool to the next.