VHDL instantiation

Entity instantiation and component instantiation

There are two ways to instantiate a module in VHDL: component instantiation and entity instantiation. Some people refer to the latter as direct instantiation.

Entity instantiation didn’t exist in the first revisions VHDL, but it has been available since VHDL’93. This is the method that I recommend unless you have specific reasons to use component instantiation.

To use the component instantiation method, you first have to declare the component in the declarative scope of where you want the module instance.

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(clk'event and clk = '1') vs rising_edge(clk)

Clk’event vs rising_edge

When you have worked with VHDL code written by many other FPGA engineers, you are bound to notice that there are two common ways to model an edge detector in VHDL. There’s the rising_edge(clk) statement, and there’s the old style clk’event and clk = ‘1’ method.

The two if-statements do the same thing once the code is on the FPGA. They postulate that whatever is inside of the if-statement happens on the rising edge of the trigger signal,

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std_logic vs std_ulogic

std_logic vs std_ulogic

VHDL includes few built-in types, but offers a number of additional types through extension packages. Two of the most widely used types are the std_logic and std_ulogic. The difference between them is that the former is resolved, while the latter isn’t.

Before we go on to investigate what it means that a type is resolved, let’s first look at the traits that the two types share in common.

Bit and boolean are part of the standard package,

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Delta cycles explained

Delta cycles explained

Delta cycles are non time-consuming timesteps used by VHDL simulators for modeling events during execution of VHDL code. They are events that happen in zero simulation time after a preceding event.

VHDL is a parallel programming language, while computers and CPUs work in a sequential manner. When a normal programming language is run, the CPU executes one instruction after the other. While in VHDL, there can be multiple sequences of logic that react to each other in ways that are not compatible with the standard computer architecture.

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One-process vs two-process vs three-process state machine

One-process vs two-process vs three-process state machine

Most of us stick to a certain way of writing a state machine. Perhaps you type out the construct that you are most familiar with without giving much thought to the alternatives. Depending on the method that you were taught when learning VHDL, you may prefer one method to another.

Over the years, I have seen many different state machine designs. To appease my curiosity, I set out to investigate the most common ways to design finite-state machines (FSMs) in VHDL.

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