VHDL includes few built-in types, but offers a number of additional types through extension packages. Two of the most widely used types are the std_logic and std_ulogic. The difference between them is that the former is resolved, while the latter isn’t.
Before we go on to investigate what it means that a type is resolved, let’s first look at the traits that the two types share in common.
Bit and boolean are part of the standard package,
Delta cycles are non time-consuming timesteps used by VHDL simulators for modelling events during execution of VHDL code. They are events that happen in zero simulation time after a preceding event.
VHDL is a parallel programming language, while computers and CPUs work in a sequential manner. When a normal programming language is run, the CPU executes one instruction after the other. While in VHDL, there can be multiple sequences of logic that react to each other in ways that are not compatible with the standard computer architecture.
Most of us stick to a certain way of writing a state machine. Perhaps you type out the construct that you are most familiar with without giving much thought to the alternatives. Depending on the method that you were taught when learning VHDL, you may prefer one method to another.
Over the years, I have seen many different state machine designs. To appease my curiosity, I set out to investigate the most common ways to design finite-state machines (FSMs) in VHDL.
