Basic VHDL quiz – Part 3

Test your progress with this VHDL quiz after completing tutorials 12-17 from the Basic VHDL Tutorial series!

1 / 7

Which statement is true about the signed type?

2 / 7

Which is equivalent to this concurrent process?

3 / 7

What value will Output have after running this code?

4 / 7

Which is true about the port declaration?

5 / 7

How will values that are passed through the generic map appear in the module?

6 / 7

What does "setup time" for a flip-flop mean?

7 / 7

Why do we normally not think about setup and hold time when designing in VHDL?

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