In the previous tutorial we learned how to delay time using the
wait for statement. We also learned about the process loop. We now know that if we let it, the process “thread” will loop within the process forever.
But what if we want to do something just once at the beginning of the process? And then loop over some other code at the end? The simplest kind of loop in VHDL can be created by using the
This blog post is part of the Basic VHDL Tutorials series.
The syntax for the simple loop is:
loop end loop;
Such a loop will continue indefinitely, or until an
exit; is encountered. The
exit statement can be used for breaking out of any loop.
This video tutorial teaches you how to create a simple loop, and how to break out of it:
The final code we created in this tutorial:
entity T03_LoopTb is end entity; architecture sim of T03_LoopTb is begin process is begin report "Hello!"; loop report "Peekaboo!"; exit; end loop; report "Goodbye!"; wait; end process; end architecture;
The output to the simulator console when we pressed the run button in ModelSim:
VSIM 2> run # ** Note: Hello! # Time: 0 ns Iteration: 0 Instance: /t03_looptb # ** Note: Peekaboo! # Time: 0 ns Iteration: 0 Instance: /t03_looptb # ** Note: Goodbye! # Time: 0 ns Iteration: 0 Instance: /t03_looptb
When running the final code in the simulator we saw that the first “Hello!” was printed to the ModelSim console. Then, the “Peekaboo!” between the
end loop; was printed. On the next line the program hit the
exit; statement, causing the program to break out of the loop. Finally, “Goodbye!” was printed. After this nothing more happens because the program is paused forever on the
We can see from the timestamps of the printouts that everything happened at 0 ns simulation time. As we learned from the previous tutorial, everything other than
wait statements consume zero time.
loopstatement implements an infinite loop
exitstatement will break out of any loop