I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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![How to use the most common VHDL type: std_logic](https://vhdlwhiz.com/wp-content/uploads/2017/07/std_logic.png)
How to use the most common VHDL type: std_logic
The most common type used in VHDL is the std_logic. Think of this type as a single bit, the digital information carried by a single physical wire. The std_logic gives us a more fine-grained control over the resources in our design than the integer type, which we have been using in the previous tutorials. Normally,…
![How to create a self-checking testbench](https://vhdlwhiz.com/wp-content/uploads/2019/04/self-checking-testbench-768x432.jpg)
How to create a self-checking testbench
A self-checking testbench is a VHDL program that verifies the correctness of the device under test (DUT) without relying on an operator to manually inspect the output. The self-checking testbench runs entirely on its own, and prints an “OK” or “Failed” message in the end. Every VHDL module should have an associated self-checking testbench. It’s…
![How to use Wait On and Wait Until in VHDL](https://vhdlwhiz.com/wp-content/uploads/2017/07/wait_on_wait_until.png)
How to use Wait On and Wait Until in VHDL
In the previous tutorial we learned the main differences between signals and variables. We learned that signals have a broader scope than variables, which are only accessible within one process. So how can we use signals for communication between several processes? We have already learned to use wait; to wait infinitely, and wait for to…
![How to use Port Map instantiation in VHDL](https://vhdlwhiz.com/wp-content/uploads/2017/09/port_map.png)
How to use Port Map instantiation in VHDL
A module is a self-contained unit of VHDL code. Modules communicate with the outside world through the entity. Port map is the part of the module instantiation where you declare which local signals the module’s inputs and outputs shall be connected to. In previous tutorials in this series we have been writing all our code…
![How to make ModelSim from Quartus Prime Lite work on Ubuntu 20.04](https://vhdlwhiz.com/wp-content/uploads/2020/05/ModelSim-Ubuntu-featured-768x432.png)
How to make ModelSim from Quartus Prime Lite work on Ubuntu 20.04
The ModelSim version that comes with Intel Quartus Prime Lite Edition is a good alternative if you want to try out VHDL simulation on your home computer. The software is available for both Windows and Linux, but Intel only supports Red Hat-based distros like CentOS Linux. Fortunately, you are just a few hacks away from…
![How to create a list of strings in VHDL](https://vhdlwhiz.com/wp-content/uploads/2020/12/string_list-768x432.jpg)
How to create a list of strings in VHDL
Text strings in VHDL are generally limited to fixed-length character arrays. That makes sense because VHDL describes hardware, and generic-length strings require dynamic memory. To define an array of strings, you have to allocate space at compile-time for the highest number of strings you want to store. And even worse, you must decide on the…
Dear Jonas
Thanks for the content, thumbs up. please keep up the good work!
Best Regards
Thanks! That’s good to hear.
You are doing a very nice job. Top quality!
Thanks! I really appreciate your comment.
Hello Jonas
You really did save me by these great videos and materials.
These tutorials are the best thing on the internet.
Thank you for creating them.
Thanks! That’s encouraging to hear. I will do my best to keep up the quality of my blog posts.
Thank you so much man you are awesome! i learnt vhdl in university but i forgot after all years. i started again working. You help me too much! i will continue to course after this beginner course. i am planning the begin beginner fast track ! please dont stop the teaching us . thank you so much! greetings from turkey 🙂
Hello, Utku. Thank you for the nice comment! I’m glad you found my blog to be helpful. I will keep the free and premium content coming your way.
Thank you for providing such great content on a subject that imo can be tricky to really understand. But you make it easy for everyone!
That’s great to hear! I will keep on creating tutorials and articles for you. ?
Dear Jonas,
I’m an electronic engineer from Morocco, currently studying for a masters degree in microelectronics and sensors in France.
You helped me a lot to remember some of the vhdl basics and get more further into it.
I worked on an academic project using basys3 and vivado for a vga controller.
Thank you very much for this great content, keep up the good work.
I’m glad you like the quiz. It’s a good way to refresh your knowledge. 🙂
Excellent learning tool
Thanks! By the way, I also use quizzes in the VHDLwhiz membership.
Great tutorials! Short and sweet!
I’ll be sure to go onto the FPGA and VHDL Fast-Track after completing the basic tutorials..
Thanks, Dale! Also, check out the VHDLwhiz Membership, which gives you multiple courses, resource items, and coding challenges and supports your success in FPGA design.
Nice quiz, only problem is sharing your score on facebook is not working.
Thanks for the feedback. I’ve created a task on this. I’ll see if I can fix it when I have the time.