Similar Posts
Logic gates interactive demo
The basic logic gates NOT, AND, NAND, OR, NOR, XOR, and XNOR are fundamental building blocks in digital circuits corresponding to Boolean operators.
Play with the switches to see how the outputs change! 😀
How to create a signal vector in VHDL: std_logic_vector
The std_logic_vector type can be used for creating signal buses in VHDL. The std_logic is the most commonly used type in VHDL, and the std_logic_vector is the array version of it. While the std_logic is great for modeling the value that can be carried by a single wire, it’s not very practical for implementing collections…
How to create a process with a sensitivity list in VHDL
You should always use a sensitivity list to trigger processes in production modules. Sensitivity lists are parameters to a process which lists all the signals that the process is sensitive to. If any of the signals change, the process will wake up, and the code within it is executed. We’ve already learned to use the…
NAND logic gates interactive demo
We can construct any other digital logic gate using only NAND gates as building blocks. This is why NAND is known as a universal gate. NAND logic is widely used as the foundation for designing digital circuits in modern integrated chips. Actually, NOR is also a universal gate, but NAND logic is more prevalent than…
How to use a function in VHDL
Functions are subprograms in VHDL which can be used for implementing frequently used algorithms. A function takes zero or more input values, and it always returns a value. In addition to the return value, what sets a function apart from a procedure, is that it cannot contain Wait-statements. This means that functions always consume zero…
What is VHDL?
In short, VHDL is a computer language used for designing digital circuits. I use the term “computer language” to distinguish VHDL from other, more common programming languages like Java or C++. But is VHDL a programming language? Yes, it is. It’s a programming language that is of no use when it comes to creating computer…
Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.
I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.
This will infer a latch:
process(InSig) is begin if InSig = '0' then OutSig <= '1'; end if; end process;This shouldn’t create any latches:
process(InSig) is begin OutSig <= '0'; if InSig = '0' then OutSig <= '1'; end if; end process;A link to the question:
https://vhdlwhiz.com/wp-content/uploads/2017/09/quiz_part-2-q6.png
Hi sir, You designed this course very well and advanced. I am happy to recommend this course to my friends.
I’m glad you enjoyed it! And thanks for taking the time to leave a nice comment.