I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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How to use Signed and Unsigned in VHDL
The signed and unsigned types in VHDL are bit vectors, just like the std_logic_vector type. The difference is that while the std_logic_vector is great for implementing data buses, it’s useless for performing arithmetic operations. If you try to add any number to a std_logic_vector type, ModelSim will produce the compilation error: No feasible entries for…
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How to create a signal vector in VHDL: std_logic_vector
The std_logic_vector type can be used for creating signal buses in VHDL. The std_logic is the most commonly used type in VHDL, and the std_logic_vector is the array version of it. While the std_logic is great for modeling the value that can be carried by a single wire, it’s not very practical for implementing collections…
![How to use a procedure in VHDL](https://vhdlwhiz.com/wp-content/uploads/2017/12/procedures.png)
How to use a procedure in VHDL
A procedure is a type of subprogram in VHDL which can help us avoid repeating code. Sometimes the need arises to perform identical operations several places throughout the design. While creating a module might be overkill for minor operations, a procedure is often what you want. Procedures can be declared within any declarative region. The…
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Stimulus file read in testbench using TEXTIO
Reading signal values from file is an alternative way of generating stimuli for the device on test (DUT). The testbench sequence and timing is hard-coded in a stimulus file that is read by the VHDL testbench, line by line. This allows you to easily change the pattern of the waveform that you want to feed…
![Basic VHDL quiz – Part 1](https://vhdlwhiz.com/wp-content/uploads/2017/08/basic_vhdl_quiz_part-1.png)
Basic VHDL quiz – Part 1
Put your skills to the test with this quiz with questions from the first part of the Basic VHDL Tutorial series.
![Generate statement debouncer example](https://vhdlwhiz.com/wp-content/uploads/2020/08/generate-statement-featured-768x432.png)
Generate statement debouncer example
The generate statement in VHDL can automatically duplicate a block of code to closures with identical signals, processes, and instances. It’s a for loop for the architecture region that can create chained processes or module instances.
Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.
I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.
This will infer a latch:
This shouldn’t create any latches:
A link to the question:
https://vhdlwhiz.com/wp-content/uploads/2017/09/quiz_part-2-q6.png
Hi sir, You designed this course very well and advanced. I am happy to recommend this course to my friends.
I’m glad you enjoyed it! And thanks for taking the time to leave a nice comment.