Basic VHDL quiz - Part 2

Basic VHDL quiz – Part 2

Test your coding skills with this VHDL quiz after completing tutorials 6-11 from the Basic VHDL Tutorial series!

If you read the blog posts, watched the videos, and did the exercises, you should be qualified to answer most of the questions in the quiz. The quiz is intentionally made a little bit challenging. If you don’t know the answer, try to use your reasoning skills to figure out the most likely answer.

Read the explanations that come after each answer. There’s some micro-learning in there.

1 / 9

What will this code print out?

MySignal=-2147483648

MySignal=0

MySignal=10

2 / 9

What will this code print out?

MySignal=0

MySignal=1

MySignal=10

3 / 9

What will this code print out?

MySignal=1

MySignal=9

MySignal=10

4 / 9

What will this code print out?

Timestep	Event
10 ns	Process 1 assigns to `Sig1`
10 ns +1 delta cycle	Process 2 assigns to `Sig2` Process 3 prints Sig1=1, Sig2=0
10 ns +2 delta cycle	Process 3 prints Sig1=1, Sig2=1

5 / 9

What will this code print out?

Timestep	Event
10 ns	Process 1 assigns to `Sig1`
10 ns +1 delta cycle	Process 2 assigns to `Sig2` Process 3 tests the expression, but goes back to sleep
10 ns +2 delta cycle	Process 3 prints Sig1=1, Sig2=1

6 / 9

Which statement is correct regarding these snippets?

The right one will cause a delta cycle delay

The left one will handle overflow better

They are logically equivalent

7 / 9

Which process is equivalent to this one?

8 / 9

What is the value of the Slv signal?

'X'

'1'

'0'

There will be a runtime error

9 / 9

What is the value of the Slv signal?

"00000000"

"10001000"

"00010001"

Your score is

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4 Comments

Lucas Lacoste says:

September 15, 2017 at 16:25

Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.

Reply
1. Jonas Julian Jensen says:
  
  September 15, 2017 at 19:55
  I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.
  
  This will infer a latch:
```
process(InSig) is
begin
    if InSig = '0' then
        OutSig <= '1';
    end if;
end process; 
```
  This shouldn’t create any latches:
```
process(InSig) is
begin
    OutSig <= '0';
    if InSig = '0' then
        OutSig <= '1';
    end if;
end process; 
```
  A link to the question:
  https://vhdlwhiz.com/wp-content/uploads/2017/09/quiz_part-2-q6.png
  Reply
Jagan Mohan says:

March 5, 2021 at 15:11

Hi sir, You designed this course very well and advanced. I am happy to recommend this course to my friends.

Reply
1. Jonas Julian Jensen says:
  
  March 5, 2021 at 15:25
  
  I’m glad you enjoyed it! And thanks for taking the time to leave a nice comment.
  
  Reply

How to make ModelSim from Quartus Prime Lite work on Ubuntu 20.04

How to create a process with a sensitivity list in VHDL

std_logic vs std_ulogic

How to use a Case-When statement in VHDL

How to create a finite-state machine in VHDL

How to use constants and Generic Map in VHDL

4 Comments

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