VHDL AXI FIFO using block RAM
This VHDL implementation of an AXI-style FIFO has generic data width and depth settings.
The axi_fifo.vhd module uses the ready/valid handshake to control the writing and reading. The FIFO synthesizes into block RAM and is compatible with the AXI/AMBA bus architecture standard.
The receiver controls the ready signal while the sender controls the valid signal. Data transfer only happens when ready and valid are ‘1’ within the same clock cycle. Thus, the AXI interface has built-in flow control.
The capacity of the FIFO is equal to
ram_depth minus one. One slot is always kept empty to distinguish between a full and an empty FIFO.
You don’t need to enable read/write memory address collision checks in the synthesis tool because the FIFO never reads from and writes to the same slot simultaneously.
entity axi_fifo is generic ( ram_width : natural; ram_depth : natural ); port ( clk : in std_logic; rst : in std_logic; -- AXI input interface in_ready : out std_logic; in_valid : in std_logic; in_data : in std_logic_vector(ram_width - 1 downto 0); -- AXI output interface out_ready : in std_logic; out_valid : out std_logic; out_data : out std_logic_vector(ram_width - 1 downto 0) ); end axi_fifo;
Click here to read more about how I created this module:
How to make an AXI FIFO in block RAM using the ready/valid handshake
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