Course: Transaction-level BFM design in VHDL using Python and AI
Create a bus functional model (BFM) for a VHDL module with multiple configuration options. Learn to make a system that generates custom BFMs for any interface variant the DUT can have.
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Course: Snake game on FPGA: Real-time VHDL simulation with GUI
Implement the classic Snake game on an FPGA with a 128×32 OLED display. Create a custom GUI to play the game in real-time using the Questa VHDL simulator.
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Course: Functional coverage-driven VHDL testbench using UVVM
Learn to implement constrained random testing methods with the UVVM VHDL verification framework. Create self-checking testbenches that discover more corner case bugs.
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Course: VHDL audio mixer using FPGA DSP blocks
Learn to create a stereo audio mixer using VHDL and multiplier (DSP) primitives in an FPGA and use a Python GUI to control the four input channels.
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Course: VHDL synthesis: From code to hardware
Learn to recognize which logic elements common VHDL design patterns describe. Think like an FPGA engineer by focusing on the underlying hardware rather than code.
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Course: Signal guards and delays in VHDL
Learn to use guarded blocks to disconnect signal drivers conditionally, and VHDL features like postponed processes and delay modeling mechanisms.
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Course: Pmod OLED controller: Display text and graphics with an FPGA
Connect an LED panel to your FPGA design to show messages or images. See how to read pixel data from a file into block RAM using VHDL.
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Course: Resolved signals and types with resolution functions in VHDL
Learn how the std_logic type handles driver conflicts internally. See how to implement custom data types with resolution functions for multiple drivers.
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Course: IoT and FPGAs: Building a cloud-connected VHDL design
Bring your VHDL project online. Set up a neat GUI dashboard using the Blynk IoT platform and a Raspberry Pi and send over-the-air (OTA) updates to your FPGA.
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Course: Cocotb introduction
Write testbenches in Python for your VHDL design with the Cocotb hardware verification framework. Learn to use Python’s asynchronous constructs in the Questa and GHDL simulators.
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Course: RISC-V processor Hello World! in VHDL
Create a reduced instruction set computer using the RISC-V processor architecture. Learn how a CPU works by implementing one in VHDL and running it on the FPGA.
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Course: MicroBlaze SoC design
$59Learn how to build a system-on-chip (SoC) design by using a MicroBlaze soft-core processor, existing IP cores, and custom VHDL modules.
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