Course: I²S audio codec ADC/DAC interface using VHDL and the Xilinx Zynq FPGA
Learn to implement the I²S protocol in VHDL and configure the ADAU1761 ADC/DAC audio codec chip on the Xilinx Zedboard with bare-metal C programming.
Showing 13–24 of 33 results
-
-
Course: I²C controller for interfacing a real-time clock/calendar module in VHDL
$59Learn to create an I²C controller (master) in VHDL and communicate with the Digilent Pmod RTCC: Real-time Clock / Calendar module.
-
Course: SPI master for reading ambient light sensor
$59Learn to create an SPI master in VHDL for reading an ambient light sensor from an FPGA. We also make an SPI slave BFM for simulating the ADC chip.
-
Course: Combining VHDL frameworks: VUnit, UVVM, and OSVVM
You don’t have to use only one VHDL verification framework. We can pick and choose the features we need and combine them to create awesome testbenches.
-
Course: VUnit for structured testbench and advanced BFM design
$59Learn to create neat testbenches and verification components using this testing framework’s VHDL libraries. Automate your simulation flow with VUnit’s Python test runner.
-
Course: UVVM introduction
The Universal VHDL Verification Methodology (UVVM) framework provides a utility library, reusable verification components, and a way to structure your VHDL testbenches.
-
Course: Advanced BFM signaling and transaction-based TB
Build a testbench that separates bit-level logic into separate modules and uses a command interface to control executor processes.
-
Course: Constrained random verification with OSVVM
Learn to achieve functional coverage in VHDL testbenches with pseudo-random DUT interactions by using the OSVVM VHDL framework.
-
Course: Image processing system and testbench design using VHDL
$59Learn to develop high-speed image processing systems using VHDL. See how to simulate pixel filters using JPG pictures in a VHDL testbench.
-
Course: Tcl scripting for FPGA engineers
$59Learn the quirks of the Tool Command Language (Tcl) and see how to create a GUI widget for controlling a VHDL testbench in Questa/ModelSim.
-
Course: Numeric types
There are many beliefs about using numeric types like signed, unsigned, integer, and real in VHDL. Let’s find out precisely what the limitations are!
-
Course: Tools for debugging VHDL designs
FPGA projects are challenging to debug, and that’s because it’s hard to understand what’s going on in the design. But once we gain insight and see the complete picture, problems often melt away.
End of content
End of content