Course: VHDL synthesis: From code to hardware
Learn to recognize which logic elements common VHDL design patterns describe. Think like an FPGA engineer by focusing on the underlying hardware rather than code.
Description
This course teaches you to recognize which digital logic your VHDL code will synthesize into. In the course, we go through 20 VHDL module examples and analyze the elaborated (RTL) and synthesized netlists in the Xilinx Vivado FPGA implementation tool.
Employers often tell me that the biggest challenge when hiring fresh VHDL designers is that the juniors don’t fully understand what kind of logic their VHDL code will produce.
More experienced FPGA professionals usually think in terms of logic rather than algorithms when coding VHDL. But there may be nuances you haven’t thought about that can affect the synthesized netlist, even if you’ve been in the game for a long time.
The course starts with some basic examples but shows more complex patterns and their differences in later lessons. The last seven of the 19 lessons focus on finite-state machines (FSMs).
Does FSM coding style influence the synthesized netlist, or is it just a matter of personal preference?
Take the course to find out! 😀
See the video below for a preview of selected lessons.
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
No FPGA board is required as this course is a pure simulation exercise.
Software used in the course
I am using Windows 11 in the course. All the other software is available for free for Windows and Linux:
- Xilinx Vivado
- Microsoft Visual Studio Code
(Any editor will do)
Course outline
The overview below shows the lessons in this course.
1 - Introduction
Have your mind set on the hardware when coding VHDL rather than thinking in terms of code and algorithms.
2 - Vivado project setup for out-of-context synthesis
The out-of-context (OOC) design flow in Vivado allows you to synthesize VHDL modules independently. We can use it to inspect their schematics without the rest of the design.
3 - For loop vector reverser
A loop in VHDL code may use zero resources if all it does is rearrange the bits in a vector.
4 - For loop Gray converter
This binary to Gray code converter module has equivalent RTL and synthesized netlists because it can't be optimized further.
5 - For loop challenge
I have a question for you. What does this code synthesize into? Let's clear up a common misconception about For loops in VHDL!
6 - For loop adder chain
Loop-based variable updates can lead to long combinational paths in the elaborated schematic, though synthesis optimization may reduce this.
7 - Equivalent While loop example
Will the elaborated and synthesized netlists look the same if we replace the For loop with a While loop? Let's find out!
8 - Loop unrolling in VHDL synthesis
9 - Generate loops
The Generate statement in VHDL can replicate parts of your design, but the synthesis outcome depends on what you put in the loop.
10 - Inferring SRLs (shift register LUTs)
You can save lots of resources if you write the shift registers in a certain way to use Xilinx's SRL primitives.
11 - Multiplexer (MUX)
It's important to recognize when your VHDL code describes multiplexers and watch out for long combinational paths.
12 - Case-When If-Elsif-Else
The elaborated design represents the logical elements described in our VHDL code, while the synthesized netlist shows the actual FPGA primitives used after optimization.
13 - FSM synchronous state implementation
Let's look at the RTL schematic for the simplest possible VHDL finite-state machine (FSM) to understand how the next-state logic works.
14 - FSM state change condition netlist
What happens when we introduce an input signal that governs the next-state logic?
15 - FSM reacting to inputs and controlling an output signal
FSMs typically have inputs driving state changes and outputs controlled by the current state. Let's examine the schematic of a simplified example.
16 - Two-process FSM with only synchronous state changes
This FSM has a combinational process controlling the outputs and next-state logic. But we have to be careful to avoid inferring latches.
17 - Two-process FSM with combinational output process
This FSM changes states in a synchronous process while it sets the outputs from a combinational process depending on the current state.
18 - Two-process FSM with a combinational next-state logic process
Here's an FSM that changes state and sets the outputs synchronously but decides the next state to go to in a combinational process.
19 - Three-process FSM
You can split the FSM code over one synchronous and two combinational processes. But how does that affect the RTL netlist?
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
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