VHDLwhiz Membership
$39This subscription-based training program supports you in becoming successful in VHDL design. Join the community and build your confidence as an FPGA engineer.
Showing 1–12 of 53 results
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Course: AXI4 master in VHDL with a DDR3 benchmark demo
Build a complete AXI4 bus master in VHDL, prove it correct with VUnit’s AXI slave models, then benchmark block RAM against DDR3 on an Arty board and see why AXI4 has bursts.
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Course: FFT on FPGA in VHDL with a real-time audio demo
$59Learn how the Fast Fourier transform (FFT) works from the ground up, then use AI to build a real-time audio spectrum analyzer in VHDL, shown live on an OLED display from an FPGA.
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Course: VGA Pong game on FPGA
$59VHDL Pong game implementation course teaching how to control a VGA monitor from an FPGA, including sync signals, gameplay, and displaying images over VGA.
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Course: VHDL text rendering with AI-assisted verification in VUnit
$59Build a Pmod OLED text renderer in VHDL with UART, backspace, and scrolling. Use AI-generated Python and VUnit to verify the design faster.
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Course: Accelerometer FPGA interface using open-source VHDL libraries
Learn to build a VHDL design with open-source RTL modules from Open Logic and OSVVM verification components, and interface the ADXL362 accelerometer chip on the Pmod ACL2 over SPI.
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Course: Regular expression VHDL engine
Learn to build a regex processing VHDL module with runtime-reconfigurable pattern matching and Unicode support, using AI-generated Python scripts to create configurations from regexes.
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Course: Bluetooth FPGA control via mobile app
Add Bluetooth connectivity to FPGA projects! Learn to control the color LEDs on your board from a phone and show VHDL signal values in the mobile app.
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Course: QSPI NOR Flash memory VHDL interface
Learn to create a Flash memory controller in VHDL for storing non-volatile data in FPGA projects. This course covers page program (write), read, and erase operations using the quad SPI bus.
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Course: Testbench reuse using VUnit and VHDL configurations for Wishbone bus verification
Learn to combine VHDL configuration statements with VUnit to maximize testbench utilization and automate test cases for Wishbone bus BFM and RTL DUTs.
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Course: Getting started with PetaLinux
$59Learn to implement system-on-chip (SoC) designs using embedded Linux for AMD Xilinx FPGAs. This course gives you the skills to succeed with PetaLinux on Zynq-7000 (ARM) devices.
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Course: Source-synchronous data bus: VHDL design and timing constraints for high-speed FPGA interfaces
Learn to design and implement high-speed source-synchronous parallel data buses in FPGAs using VHDL.
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