Course: MicroBlaze V with Vitis Unified
$69
Build a system-on-chip (SoC) with the MicroBlaze V, AMD’s RISC-V soft processor. Connect your own VHDL modules over AXI, handle interrupts from your hardware, and stream audio over Ethernet with lwIP.
Description
Plug a music source into the Pmod I2S2, start a Python script on your PC, and the music arrives over Ethernet as a WAV file while you change the volume from the serial terminal or with the push buttons on the board. Inside the FPGA, a MicroBlaze V soft processor runs the C program out of DDR3 memory, our own VHDL modules sit on the AXI bus, and an audio mixer does the signal processing in its own clock domain.
The MicroBlaze V is the new soft processor from AMD. It runs the RISC-V instruction set, so you get the standard GCC toolchain and code that isn’t tied to one vendor, and you program it in Vitis Unified, the IDE that replaced the classic Vitis. If you took my earlier MicroBlaze course, the block design will look familiar from the outside. The processor inside it and the software tools are new, and so is most of this course.
The first half builds a standard system from AMD IP and templates: the block design with DDR3 and UART, the Vitis platform and Hello World, the memory layout and the linker script, Ethernet, and the lwIP echo server that answers pings from your PC. The second half puts our own hardware in it: two AXI4-Lite register modules written in VHDL, the C code that reads them, an interrupt from our own logic, and the audio mixer with its AXI wrapper, streaming over TCP/IP.
Add a second course for half price. The MicroBlaze SoC design course covers the classic MicroBlaze and the classic Vitis IDE, for designs built on the original processor. Getting started with PetaLinux takes the other route to a system-on-chip, with embedded Linux on the Zynq’s ARM cores.
When you buy this course, you can add either of them, or both, to your order for 50% off each.
Click the Buy course button at the top of this page to see the offer on the checkout page.
This course is not about typing VHDL. It’s about managing a soft processor project where the hardware in Vivado and the software in Vitis have to agree with each other. So every time we add something to the block design, a module, an address, or an interrupt input, we follow it to the file in Vitis where it ends up. The Address Editor, the XSA, the device tree, xparameters.h, and the linker script. When something doesn’t work, that’s where you look.
The register modules, the AXI wrapper, the C programs, and the Python scripts were written with an AI assistant from my specifications, then reviewed, simulated where a testbench exists, and tested on the board. The mixer core, the debouncer, and the reset synchronizer are handwritten VHDLwhiz modules. We read through every file together in the lessons, and all of it is included for download, so you don’t need an AI tool to follow the course.
The audio mixer comes from my VHDL audio mixer course, and the classic MicroBlaze with the IP Packager is covered in my MicroBlaze SoC design course. You don’t need to take those first, as everything you need is available for download in this course.
You can follow every lesson in Vivado and Vitis without a board, up to the point where we program the FPGA, and I show the results on my board anyway. You need the hardware below to run the system yourself.
Hardware used in the course
- Arty A7-100T: Artix-7 FPGA Development Board (SKU: 410-319-1)
Resellers: Digilent, Mouser, DigiKey
(I use the Arty A7-35T in the course, which Digilent has retired. The A7-100T is the same board with a bigger FPGA. Any AMD board with DDR3 memory and an Ethernet port works for the processor part, with the constraint file for your board.) - Pmod I2S2: Stereo Audio Input and Output (SKU: 410-379)
Resellers: Digilent, Mouser, DigiKey, RS Electronics
(For the audio lessons. The mixer supports up to four of them, one per Pmod connector, but one is enough for the course.) - An Ethernet cable
(From the board to a free port on your router, or to a USB-to-Ethernet adapter on your PC as I do in the course) - A micro USB cable
(For programming the FPGA and the UART connection to the serial terminal) - A mini-jack male-to-male audio cable
(From the music source to the Pmod I2S2 line in. I play music from my computer. A speaker on the line out is optional, since the stream goes to the PC.)
Software used in the course
I use Windows 11 in the course. All the other software is available for free for Windows and Linux:
- AMD Vivado and Vitis Unified
(Both come from the AMD Unified Installer. The free editions are enough.) - Questa – Intel FPGA Edition (includes Starter Edition)
(Optional, for the two testbenches that come with the downloads. Any version of ModelSim or QuestaSim will work.) - Microsoft Visual Studio Code
(Any editor will do) - Python 3
(For the scripts on the PC that test the Ethernet speed and capture the audio stream. They use only the standard library.)
This course is also available in the VHDLwhiz Membership.
The difference is that when you purchase this product, you get permanent access to the course, while the membership charges a monthly fee to access the content.
Course outline
The overview below shows the lessons in this course.
1 - Introduction
Welcome to the course! We'll build a complete system-on-chip around the MicroBlaze V soft processor on the Arty A7, with our own VHDL modules on the AXI bus and audio streaming over Ethernet.
2 - MicroBlaze V block design in Vivado
We'll create a Vivado project with the first version of our block design. After adding the MicroBlaze V, DDR3 memory controller, and a UART core, we export the hardware to Vitis.
3 - Vitis platform and Hello World
Let's move from Vivado to Vitis. We'll look inside the XSA file, create the platform component and a Hello World application, and see the output from the MicroBlaze V in the serial monitor.
4 - Memory layout and the linker script
See how the MicroBlaze V finds its program, what the linker script says about DDR3 and block RAM, and how to size the heap and stack. We test the limits with malloc and recursion in C.
5 - Ethernet and the 25 MHz PHY clock
In this lesson, we add AXI EthernetLite and an AXI Timer to the MicroBlaze V block design in Vivado, then generate the 25 MHz Ethernet PHY clock and work around a MIG clock rounding error.
6 - lwIP echo server over Ethernet
Let's get TCP/IP running on the MicroBlaze V with the lwIP echo server. We'll set up the board support package in Vitis, ping the Arty A7 over Ethernet, and measure the speed with Python.
7 - Custom AXI4-Lite VHDL modules
We'll connect our own VHDL modules to the MicroBlaze V over AXI4-Lite. After reviewing the counter and push-button module with an interrupt, we add both to the block design.
8 - Custom AXI registers and interrupts in C
Let's control our VHDL modules from C in Vitis. We read a 64-bit counter over AXI4-Lite, measure how long a register read takes, and handle push-button presses with an interrupt.
9 - Audio mixer VHDL in the block design
In this lesson, we start the audio streaming demo in Vivado. We add the VHDL audio mixer with its AXI4-Lite wrapper to the block design and generate the 24.576 MHz clock for the Pmod I2S2.
10 - The audio stream application in C
We'll build the audio stream application in Vitis from the lwIP echo server template. The C code streams the mix over TCP, takes volume commands over UART, and handles the button interrupts.
11 - The finished system on the board
Let's test the finished system on the board. We capture the audio stream from the MicroBlaze V to a WAV file with a Python script and change the volume over UART and with the buttons.
This course is also available in the VHDLwhiz Membership.
The difference is that when you purchase this product, you get permanent access to the course, while the membership charges a monthly fee to access the content.
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