Course: RISC-V processor Hello World! in VHDL

Create a reduced instruction set computer using the RISC-V processor architecture. Learn how a CPU works by implementing one in VHDL and running it on the FPGA.

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Description

This course teaches how to create a RISC-V reduced instruction set computer in VHDL and write a C program to run on it. After compiling the C code using GCC, we will run the program on our custom CPU and see the “Hello World!” output on the screen.

We implement the ALU ( arithmetic logic unit), the decoder, the program memory, and just enough instructions in the control unit to run the Hello World program on our processor.

See the video below for a preview of selected lessons.

This course is only available in the VHDLwhiz Membership.

The membership subscription gives you access to this and many other courses and VHDL resources.

You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.

Hardware used in the course

Software used in the course

I am using Windows 11 in the course. All the other software is available for free for Windows and Linux:

Course outline

Number of lessons:
19
Average video duration:
8m28s
Total video duration:
2h41m

The overview below shows the lessons in this course.

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1 - Introduction

Welcome to this exciting course about creating a RISC-V CPU that will run your Hello World C program.

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2 - Top-level diagram

This flow chart shows the VHDL modules we will create and the data flow in the design.

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3 - Top-level module and testbench

I have prepared a VHDL project with everything except the RISC-V CPU to help you get started.

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4 - Compiling the C program using GCC

To get the instructions for loading into memory, we must compile the C code as a bare-metal program and disassemble it.

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5 - Loading the program into block RAM

Let's create the memory module and load the instruction words and data from the hex file.

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6 - Slicing the instruction word

We must extract the opcode, function fields, source and destination registers, and the immediates from the instruction word.

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7 - Decoder

The RISC-V RV32I instruction set listing has all the information needed to determine which operation it is.

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8 - Arithmetic logic unit (ALU)

The (ALU) performs basic arithmetic and logical operations, such as addition, subtraction, and bit shifting.

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9 - Defining the control unit module

The control unit is the CPU component that manages and coordinates all the processor operations by executing instructions.

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10 - Control unit finite-state machine

We will use an FSM with nested case statements to fetch and execute instructions.

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11 - Debug printouts in RTL code

You can include debugging code like report statements and asserts in production code.

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12 - ADDI (add Immediate)

This instruction adds an immediate to a register value and stores the result in a register.

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13 - LUI (load upper immediate)

LUI loads the top 20 bits of the destination register with a value from the U-immediate.

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14 - SB (store byte)

Write a byte anywhere in the memory—or to the memory-mapped UART interface, in our case

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15 - LBU (load byte unsigned)

We must slice the correct eight bits from the memory output to load only one byte.

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16 - BEQ & BNE (branch if equal/not equal)

These instructions compare two registers and conditionally jump by changing the program counter.

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17 - JAL and JALR (jump and link (register))

These unconditional jumps will update the program counter and save the return address in a register.

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18 - Implementing the design on the FPGA

We'll implement the top-level design on the Digilent Arty S7-50 board with a Xilinx Spartan-7 FPGA using Vivado.

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19 - Hello World!

Let's test on the FPGA to see our C program running our custom RISC-V CPU.

This course is only available in the VHDLwhiz Membership.

The membership subscription gives you access to this and many other courses and VHDL resources.

You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.

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