VHDL dual 7-segment display controller
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This VHDL module shows a decimal value from 0 to 99 on the Pmod SSD: Seven-segment Display from Digilent or similar dual 7-segment display.
Description
The seg7.vhd module displays a number from 0 to 99 on the Pmod SSD: Seven-segment Display from Digilent or similar. The Pmod SSD can only illuminate one digit at a time, but by quickly alternating between the two, the numbers will appear as static to the human eye.
The refresh rate is configurable through generics.
Entity
entity seg7 is generic ( -- refresh_hz = (2 ** clk_cnt_bits) / clk_hz clk_cnt_bits : integer ); port ( clk : in std_logic; rst : in std_logic; value : in integer range 0 to 99; segments : out std_logic_vector(6 downto 0); digit_sel : out std_logic ); end seg7;
Main article
Click here to read more about how I created this module:
Dual 7-segment display FPGA controller
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License agreement
MIT License
Copyright (c) 2024 Jonas Julian Jensen
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