VHDL ring buffer FIFO in block RAM
This VHDL implementation of a ring buffer FIFO has generic data width and depth settings.
The ring_buffer.vhd module implements a FIFO in block RAM. The width and depth of the circular buffer are configurable through generics. In addition to the read and write ports, the entity contains
full flags and a
fill_count integer output. These are for flow control.
entity ring_buffer is generic ( RAM_WIDTH : natural; RAM_DEPTH : natural ); port ( clk : in std_logic; rst : in std_logic; -- Write port wr_en : in std_logic; wr_data : in std_logic_vector(RAM_WIDTH - 1 downto 0); -- Read port rd_en : in std_logic; rd_valid : out std_logic; rd_data : out std_logic_vector(RAM_WIDTH - 1 downto 0); -- Flags empty : out std_logic; empty_next : out std_logic; full : out std_logic; full_next : out std_logic; -- The number of elements in the FIFO fill_count : out integer range RAM_DEPTH - 1 downto 0 ); end ring_buffer;
Click here to read more about how I created this module:
How to create a ring buffer FIFO in VHDL
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