VHDLwhiz Membership
$39This subscription-based training program supports you in becoming successful in VHDL design. Join the community and build your confidence as an FPGA engineer.
Showing 1–12 of 13 results
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Course: VHDL audio mixer using FPGA DSP blocks
Learn to create a stereo audio mixer using VHDL and multiplier (DSP) primitives in an FPGA and use a Python GUI to control the four input channels.
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Course: Resolved signals and types with resolution functions in VHDL
Learn how the std_logic type handles driver conflicts internally. See how to implement custom data types with resolution functions for multiple drivers.
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Course: IoT and FPGAs: Building a cloud-connected VHDL design
Bring your VHDL project online. Set up a neat GUI dashboard using the Blynk IoT platform and a Raspberry Pi and send over-the-air (OTA) updates to your FPGA.
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Course: I²C controller for interfacing a real-time clock/calendar module in VHDL
$59Learn to create an I²C controller (master) in VHDL and communicate with the Digilent Pmod RTCC: Real-time Clock / Calendar module.
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Course: SPI master for reading ambient light sensor
$59Learn to create an SPI master in VHDL for reading an ambient light sensor from an FPGA. We also make an SPI slave BFM for simulating the ADC chip.
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Course: Tcl scripting for FPGA engineers
$59Learn the quirks of the Tool Command Language (Tcl) and see how to create a GUI widget for controlling a VHDL testbench in Questa/ModelSim.
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Course: Clock divider
Learn to use Xilinx’s MMCMs to derive clocks, create a gated clock, and write a run-time configurable clock divider without sacrificing timing using the BUFGCE primitive.
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Course: Run-length encoding in VHDL
$59Learn how to implement run-length compression in VHDL! We will create encoder and decoder modules, a self-checking testbench, and implement it on an FPGA board.
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Course: Protected type string list
Learn to create a dynamic string list in VHDL based on Python’s list class. Use a protected type to store any number of strings of any length during simulation.
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Course: Makefile-based workflow for Lattice
Learn to convert a Lattice iCEcube2 GUI project into a Makefile-based workflow. Manage your FPGA implementation project entirely from the command line.
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Course: Script-based workflow
Learn how to structure a VHDL project with multiple submodules. Use scripts to derive the compile order, launch simulations, and run regression tests.
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