Course: Makefile-based workflow for Lattice
Learn to convert a Lattice iCEcube2 GUI project into a Makefile-based workflow. Manage your FPGA implementation project entirely from the command line.
Description
Graphical user interface (GUI) tools are great for setting up an FPGA project. With the guidance of the “wizard” setup assistant, getting started quickly is easy.
However, a script-based design flow is more convenient as the project evolves beyond the initial stage. That’s especially true if several people are collaborating on the code.
Here are some of the reasons why companies prefer scripts and Makefiles:
- You can commit a script to your version control system, meaning that someone else can check out the code and reproduce your results without knowing which button sequences to click in the GUI.
- The script serves as documentation. You can always go back and find out exactly how each implementation step was started.
- It saves time in the long run. You can’t possibly click checkboxes and hit buttons as fast as a Makefile can start the programs to get you the results.
In this course, we grab a GUI-based Lattice iCEstick FPGA project from the membership portal and port it to a script-based flow. We will use a Makefile because it’s an industry standard that has existed for over 40 years, and it’s not going away anytime soon.
I’m showing you how to do it for Lattice FPGAs, but the method is the same for other FPGA vendors. And even though Make is a Unix tool, it works just as well with Windows (I’m using Windows).
Finally, we will have an FPGA project we can manage entirely from the command line. For example, by typing, make synth to synthesize, make hw to generate the bitfile, or make prog to program the FPGA.
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
Hardware used in the course
Software used in the course
I am using Windows in the course. All the other software is available for free for Windows and Linux:
⚠ Warning: additional cost!
Lattice Semiconductor now charges over $350/year for the iCEcube2 software used in this course. It was free until April 2024.
- Lattice iCEcube2 Design Software
(Or the implementation software for your FPGA architecture) - Microsoft Visual Studio Code
(Any editor will do) - The GNU Make tool
Installed through Chocolatey in Windows or pre-installed in Linux - Git SCM
Course outline
The overview below shows the lessons in this course.
1 - Why use Makefiles
Makefiles have been around for over 45 years, and they are not going away anytime soon.
2 - Install the tools and get the example project
Set up your development environment quickly and easily.
3 - Extract the commands from the iCEcube2 GUI
We can find the backend commands that the GUI uses in the transcript window.
4 - Create implementation Makefile targets
In this lesson, we convert the extracted commands to targets and recipes in the Makefile.
5 - Fix the synth target
The synthesis tool needs a few environment variables set to run without errors.
6 - Fix the implementation targets
Let's see if we can get all the other Makefile targets working.
7 - Program the FPGA using Make
We can invoke the Diamond programmer from the Makefile too.
8 - Replace absolute paths with variables
Let's clean up this Makefile by using variables instead of hard-coded paths.
9 - Synth prerequisite
We need to resynthesize whenever any of the source files change.
10 - Implementation prerequisites
To rerun recipes only when the prerequisites have changed, we need to define new targets based on actual file names.
11 - Clean target
Every Makefile should have a target that deletes the output and temporary files.
12 - Help target
Let's make a nice help menu and set it as the default Makefile target.
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
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