Course: Testbench reuse using VUnit and VHDL configurations for Wishbone bus verification
Learn to combine VHDL configuration statements with VUnit to maximize testbench utilization and automate test cases for Wishbone bus BFM and RTL DUTs.
Description
This course is about the Wishbone bus, the VUnit framework, and testbench reuse using VHDL configuration statements.
We will develop two bus functional models (BFMs) and two RTL modules that support pipelined block transfers through the open-source Wishbone communication bus specification.
By using VHDL configuration statements, we’ll repurpose a single testbench to cross-test the modules against each other, effectively turning one testbench file into four different testbenches.
See the video below for a preview of selected lessons.
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
No FPGA board is required as this course is a pure simulation exercise.
Software used in the course
I am using Windows 11 in the course. All the other software is available for free for Windows and Linux:
- Questa – Intel FPGA Edition(includes Starter Edition)
(Any version of ModelSim or QuestaSim will work) - The VUnit open-source VHDL unit testing framework
- Microsoft Visual Studio Code
(Any editor will do)
Course outline
The overview below shows the lessons in this course.
1 - Introduction
Here's what you will get from this course!
2 - The Wishbone standard
We'll implement Wishbone master and slave modules supporting pipelined block transfers. Let's review the specification PDF to clarify how they shall work.
3 - VUnit testbench setup
Since we're practicing test-driven development in this course, we'll start by creating the testbench. Let's use the VUnit testing framework for that.
4 - Examine VUnit VCs
The VUnit framework includes several verification components, including Wishbone masters and slaves. Maybe we can use them in our testbenches.
5 - Testing the VUnit VCs
Let's create a testbench using only the VUnit Wishbone master and slave modules. Then, we can evaluate these modules and decide if we can use them in our project.
6 - Wishbone self-checking testbench
Using VUnit's bus master verification component interface (VCI), we'll set up the main testbench to perform a burst write and readback through the Wishbone master in every test case.
7 - Master BFM implementation
The Wishbone master bus functional model (BFM) must respond to bus master VCI procedure calls from the main testbench and communicate with the slave module.
8 - Slave BFM implementation
The Wishbone slave BFM will be a simple data storage module. It shall support pipelined block cycles and use VUnit's memory model internally.
9 - Slave stall pattern testing
Use this method to autogenerate test cases to check that the Wishbone master responds correctly to stall signal backpressure from the slave.
10 - Master strobe pattern testing
The Wishbone master can also throttle the data rate by lowering the strobe signal. We need to verify that the slave module handles that correctly.
11 - Wishbone master and slave RTL modules
Creating the synthesizable Wishbone modules is easier once you have test cases in the VUnit testbench. Here are the VHDL modules for which we made the testbench.
12 - Slave RTL module testbench configuration
We'll use VHDL's configuration construct to swap the slave BFM instance for the real Wishbone slave to reuse the same testbench to verify the RTL module.
13 - Master wrapper and testbench configuration
To reuse the testbench for the synthesizable Wishbone master RTL module, we must create a VHDL wrapper to control it with VUnit's verification component interface (VCI).
14 - System testbench configuration
Finally, let's set up a testbench configuration that uses only the RTL master and slave modules. It's easy with VUnit and VHDL configuration statements!
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
Reviews
There are no reviews yet.