Course: AXI4 master in VHDL with a DDR3 benchmark demo

Description

Flip a switch to select on-chip block RAM or the DDR3 chip, set the burst length with three more switches, and press a button. The FPGA fills the memory with a test pattern, reads it back, checks every word, and prints one line over UART with the cycle count and the throughput in MB/s. Every operation ends with PASS, or with FAIL and the address where the data went wrong.

But this course is about more than a memory benchmark. The real subject is AXI4, the memory-mapped bus that the FPGA world runs on. It’s the interface on nearly every IP block in Vivado, on the DDR controller, and between the processor and the fabric in every SoC design. Most of us only ever connect AXI in the block diagram and let the tools handle the protocol. In this course, you implement it yourself.

We write one substantial VHDL module by hand: the bus master (manager). It has a control state machine, a burst sequencer that splits any transfer into legal bursts and respects the 4 KB boundary rule, a pattern generator with a per-beat read checker, and cycle counters that turn every operation into a measurement. Everything around it comes from the Vivado IP catalog: SmartConnect, the AXI BRAM controller, and the MIG DDR3 memory controller. That split is deliberate, because writing one module and integrating it with professional IP is exactly how you will meet AXI at work.

The master is fully verified before Vivado even opens. VUnit’s AXI slave (subordinate) verification components act as a memory-backed slave that checks the protocol rules for us: the handshakes, the WLAST placement, and the 4 KB rule, even under random stalls on every channel. The complete testbench with twelve test cases is included as a download, and we break the data pattern on purpose to prove that the checker actually checks.

The payoff is the burst-length sweep on real hardware. At burst length 1, both memories crawl at around 11 MB/s. At burst length 128, the same design moves data at over 260 MB/s, closing in on the theoretical ceiling of the 32-bit bus. When the table builds up line by line in your serial terminal, you’ll know exactly why AXI4 has bursts, because your own design measured it.

The testbench runs on the VUnit framework. You don’t need to take my VUnit course first, as I will go through the testbench structure with you. But it’s the natural next step if you want to go deeper into the verification components.

You can follow the first nine lessons in simulation with no hardware at all, and the verification story is complete without a board. You need the hardware below to run the DDR3 benchmark on your own desk.

Hardware used in the course

• Arty S7-25: Xilinx Spartan-7 FPGA (SKU: 410-352-25)
  Resellers: Digilent, Mouser, DigiKey
  (Other AMD/Xilinx 7-series boards with DDR3 also work if you select the matching board files and constraint file.)

Software used in the course

I use Windows 11 in the course. All the other software is available for free for Windows and Linux:

• Questa – Intel FPGA Edition(includes Starter Edition)
  (Any version of ModelSim or QuestaSim will work)
• AMD Vivado
  (The free edition covers the Arty boards)
• The VUnit test framework
  (Installed with a single pip command; the course shows the setup)
• Python 3
  (VUnit runs on it; no Python programming required)
• Microsoft Visual Studio Code
  (Any editor will do)
• YAT – Yet Another Terminal
  (Any serial (UART) terminal program will do)

Course outline

The overview below shows the lessons in this course.