Course: Clock divider
Learn to use Xilinx’s MMCMs to derive clocks, create a gated clock, and write a run-time configurable clock divider without sacrificing timing using the BUFGCE primitive.
Description
Use the FPGA’s built-in clocking resources when possible. In Xilinx FPGAs, that means the MMCM/PLL primitives.
But it helps to know the alternatives because you don’t always get what you need from Clocking Wizard. For example, if the clock frequency shall be runtime configurable or if the frequency is too slow for the PLL.
In this course, we use only Xilinx Vivado to simulate, synthesize, and implement a derived clock signal in three different ways. I will walk you through the timing reports and write constraints for the slower clock where needed.
Topics covered in this course:
- Creating a clock divider using an MMCM
- Writing a custom clock divider in VHDL
- Using a BUFGCE primitive to improve the timing characteristics
The BUFGCE will only let through a complete clock pulse if CE already is active when the rising edge arrives. It ignores changes to CE between clock edges. Thus, the latency through any flip-flops in the clock divider before the BUFGCE doesn’t matter.
This behavior enables us to create a clock divider using VHDL without the timing issues associated with gated clocks. I’ll show you how to achieve that in the final lesson.
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
Hardware used in the course
- Xilinx (Avnet) ZedBoard (SKU: AES-Z7EV-7Z020-G)
Resellers: Avnet, Digilent, Farnell, Newark, Mouser, DigiKey
I’ll implement the demo project on the ZedBoard just to show that it’s a real design that works on the FPGA, but you don’t need to have this or any board. All the work is done in Vivado.
Software used in the course
I am using Windows in the course. All the other software is available for free for Windows and Linux:
- Xilinx Vivado
- Microsoft Visual Studio Code
(Any editor will do)
Course outline
The overview below shows the lessons in this course.
1 - Introduction
Let's talk about the project at hand what the best way to create a clock divider is.
2 - Example design
Let me present the demo project that we will use in this tutorial series.
3 - Project creation and simulation in Vivado
We will use Xilinx Vivado for synthesis and simulation.
4 - First implementation
It's time to run the design through synthesis and place and route (PAR).
5 - Using an MMCM
I recommend using a Mixed-Mode Clock Manager (MMCM) module to generate derived clocks if you can.
6 - Clock divider VHDL module
Let's try using a VHDL module as a clock divider to derive the 1 MHz clock.
7 - Flip-flip clock divider implementation
Before we can trust this design, we have to dig into the timing report and pay special attention to the clock domain crossing paths.
8 - Using a BUFGCE primitive to create a slower clock
A better way to create a slow clock controlled by flip-flops is to utilize a global clock buffer with clock enable (CE).
This course is only available in the VHDLwhiz Membership.
The membership subscription gives you access to this and many other courses and VHDL resources.
You pay monthly to access the membership and can cancel the automatic renewal anytime. There is no lock-in period or hidden fees.
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