Course: Clock divider
Learn to use Xilinx’s MMCMs to derive clocks, create a gated clock, and write a run-time configurable clock divider without sacrificing timing using the BUFGCE primitive.
Showing 25–36 of 46 results
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Course: Run-length encoding in VHDL
$59Learn how to implement run-length compression in VHDL! We will create encoder and decoder modules, a self-checking testbench, and implement it on an FPGA board.
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Course: Protected type string list
Learn to create a dynamic string list in VHDL based on Python’s list class. Use a protected type to store any number of strings of any length during simulation.
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Course: Delta cycles in-depth
Understanding how delta cycles work in VHDL is key to becoming proficient in FPGA design. This course teaches you how signal scheduling works in simulation.
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Course: Makefile-based workflow for Lattice
Learn to convert a Lattice iCEcube2 GUI project into a Makefile-based workflow. Manage your FPGA implementation project entirely from the command line.
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Course: Script-based workflow
Learn how to structure a VHDL project with multiple submodules. Use scripts to derive the compile order, launch simulations, and run regression tests.
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Sale!
Dot Matrix VHDL and FPGA Course
Original price was: $297.$148.50Current price is: $148.50.Learn how to create a VHDL project from scratch with self-checking testbenches. Dot Matrix is the most extensive course VHDLwhiz has ever made.
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Course: FPGA and VHDL Fast-Track
$27Hands-On for Absolute Beginners. Understand the basics of FPGA development using VHDL in a few evenings!
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VHDL registers UART test interface generator
$39This tool generates a VHDL module and a Python script to read from or write to any number of custom FPGA registers using UART.
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VHDL package: Binary file reader/writer
$29These VHDL packages provide a user-friendly interface for binary file access in simulation to read or write bit vectors of any length.
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VHDL package: WAV audio file reader/writer
$29These VHDL packages read and write WAV audio files. They provide a user-friendly way to run VHDL simulations on audio processing modules.
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VHDL module: AXI-style UART
$15This project contains three general-purpose, AXI compatible, universal asynchronous receiver-transmitter (UART) modules.
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