I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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Logic gates interactive demo
The basic logic gates NOT, AND, NAND, OR, NOR, XOR, and XNOR are fundamental building blocks in digital circuits corresponding to Boolean operators.
Play with the switches to see how the outputs change! 😀
How to stop simulation in a VHDL testbench
How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run. The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving…
What is VHDL?
In short, VHDL is a computer language used for designing digital circuits. I use the term “computer language” to distinguish VHDL from other, more common programming languages like Java or C++. But is VHDL a programming language? Yes, it is. It’s a programming language that is of no use when it comes to creating computer…
How to use Port Map instantiation in VHDL
A module is a self-contained unit of VHDL code. Modules communicate with the outside world through the entity. Port map is the part of the module instantiation where you declare which local signals the module’s inputs and outputs shall be connected to. In previous tutorials in this series we have been writing all our code…
Why you always need a testbench
As most hardware engineers, I started off my computer science career by learning a sequential programming language. The first language I learned at the University of Oslo was Java. While it’s not considered to be the most exciting language today, at the time, Java was at the pinnacle of its popularity. The engineers who built…
How to delay time in VHDL: Wait For
In the previous tutorial we learned that a process can be thought of as a program thread. We also learned that a wait; statement causes the program to pause indefinitely. But is there a way to make a program wait for any other time value than forever? If we remove the wait; altogether and try…

Dear Jonas
Thanks for the content, thumbs up. please keep up the good work!
Best Regards
Thanks! That’s good to hear.
You are doing a very nice job. Top quality!
Thanks! I really appreciate your comment.
Hello Jonas
You really did save me by these great videos and materials.
These tutorials are the best thing on the internet.
Thank you for creating them.
Thanks! That’s encouraging to hear. I will do my best to keep up the quality of my blog posts.
Thank you so much man you are awesome! i learnt vhdl in university but i forgot after all years. i started again working. You help me too much! i will continue to course after this beginner course. i am planning the begin beginner fast track ! please dont stop the teaching us . thank you so much! greetings from turkey 🙂
Hello, Utku. Thank you for the nice comment! I’m glad you found my blog to be helpful. I will keep the free and premium content coming your way.
Thank you for providing such great content on a subject that imo can be tricky to really understand. But you make it easy for everyone!
That’s great to hear! I will keep on creating tutorials and articles for you. ?
Dear Jonas,
I’m an electronic engineer from Morocco, currently studying for a masters degree in microelectronics and sensors in France.
You helped me a lot to remember some of the vhdl basics and get more further into it.
I worked on an academic project using basys3 and vivado for a vga controller.
Thank you very much for this great content, keep up the good work.
I’m glad you like the quiz. It’s a good way to refresh your knowledge. 🙂
Excellent learning tool
Thanks! By the way, I also use quizzes in the VHDLwhiz membership.
Great tutorials! Short and sweet!
I’ll be sure to go onto the FPGA and VHDL Fast-Track after completing the basic tutorials..
Thanks, Dale! Also, check out the VHDLwhiz Membership, which gives you multiple courses, resource items, and coding challenges and supports your success in FPGA design.
Nice quiz, only problem is sharing your score on facebook is not working.
Thanks for the feedback. I’ve created a task on this. I’ll see if I can fix it when I have the time.