How to create your first VHDL program: Hello World!

When learning a new programming language, I always like to start by learning how to print. When you master outputting “Hello World!”, you know that you’ve got the environment working. It also shows you the basic skeleton of the language, the bare minimum code required to produce any output.

You might be thinking: but VHDL is a hardware description language, how can it output any text at all? You would need a screen connected to an FPGA or something and all sorts of logic in between, and that wouldn’t be simple at all. While all this is true, let’s forget about FPGA’s and ASIC’s just for a moment and focus our attention on the VHDL language.

This blog post is part of the Basic VHDL Tutorials series.

VHDL can be thought of as a parallel programming language, and therefore we can use this programmer’s approach for learning it. Since we use the language to describe digital circuits, the only way we can run it on our computer is by using a simulator, and the simulator is definitely capable of outputting “Hello World!” to the screen.

How to install a VHDL simulator and editor for free

Exercise

This video tutorial will show you how to create your very first VHDL program:

The final code that we created:

entity T01_HelloWorldTb is
end entity;
 
architecture sim of T01_HelloWorldTb is
begin
 
    process is
    begin
 
        report "Hello World!";
        wait;
 
    end process;
 
end architecture;

The output to the simulator console when we pressed the run button in ModelSim:

VSIM 2> run
# ** Note: Hello World!
#    Time: 0 ns  Iteration: 0  Instance: /t01_helloworld

Analysis

On the first two lines, we declared the entity. The entity of a module declares its inputs and outputs. For it to be possible to run a module in a simulator, it cannot have any inputs or outputs. Therefore our module doesn’t have anything other than an empty entity declaration.

Next, we declared the architecture of the module. While the entity is a module’s interface to the outside world, the architecture is its internal implementation. A module may have several architectures which may be used with the same entity. I wouldn’t worry too much about these things at this point as they are advanced VHDL features.

Inside of the architecture, we declared a process. For now, we can think of a process as a thread in our program, where things happen sequentially.

Inside the process, we print “Hello World!” using the report keyword. On the next line, there is a single wait;. When the simulator hits this line, nothing more is going to happen. The process will wait here forever.

When we simulated this design in ModelSim, we could see that “Hello World!” was printed to the console output. After that, nothing more happened.

Takeaway

• You can think of a process as a program thread
• The report statement prints text to the simulator console
• Execution of a process will wait forever on a wait; statement

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