We don't have to think about setup and hold time inside of the FPGA because this is handled automatically by the software tools in a later process called place and route.

However, you will have to consider setup and time constraints when interfacing external devices. Then you may have to design your VHDL code to avoid setup and hold time violations on the external interface.

The For loop iterates 10 times. The wait for 0 ns; line directly after the signal assignment ensures that its value is updated between each iteration.

Every process that is declared using only process is begin has to contain at least one Wait statement.

The process will print at 0 ns simulation time and then every 10 ns. By default, Questa/ModelSim simulates 100 ns every time we press the Run button, but that's an arbitrary value that can easily be changed.

The leftmost bit of signed types is the sign bit. If it's '1', the number is negative. If it's '0', the number is positive. Because one bit is used for the sign bit, signed types cannot represent as high values as an unsigned type with the same bit length:

The range 0 to 0 includes all numbers from 0 to 0.

Thus, the For loop will iterate once:

There is no Wait statement inside the For loop, and therefore it completes in zero time in the simulator.

We are here talking about the time within the simulation environment, and not the time that passes while you wait for your computer to load and run the simulation.

The two code snippets do exactly the same thing. Use whichever one you like.

The MySignal <= MySignal + 1; line schedules a new value onto MySignal, its old value plus 1. There is no Wait statement inside of the For loop. Therefore, the signal's value doesn't get updated between the 10 iterations.

Signal values are scheduled for the next time step. If there are several assignments before the next timestep, the last assignment "wins".

The wait for 0 ns; line causes MySignal to update its value before the report statement and the value 1 is printed. Waiting for 0 nanoseconds is a common trick in VHDL for updating signal values without letting any simulation time pass.

1. There is no reset of the State signal
2. Therefore, the State signal will get the default value at first
3. The default value is always the leftmost value from the type declaration
4. This causes the module to start up in the Armed state

(The ordering of the values in the t_State type declaration is also questionable. The Safe state should have been the leftmost state. Good job if you spotted that!)

The initial value of MySignal is 0.

The For loop will execute the MySignal <= MySignal + 1; line 10 times.

Signal values only become effective when the process pauses, for example, at a Wait statement. There is no Wait statement in the For loop or before the report statement. Therefore, the value of MySignal is still 0 when the report statement is executed.

At 10 nanoseconds the first process will change the Sig1 signal. This will trigger the second process to wake up and change Sig2.

The third process is sensitive the both Sig1 and Sig2. When either of them changes, the process will wake up and the printout will appear.

Even if everything happens at exactly 10 ns simulation time, the third process will be woken up twice, once by each of the signals. This is not an error. It happens because the VHDL simulator operates with event scheduling timesteps called delta cycles.

When the first process changes Sig1 it causes the other two processes to wake up simultaneously at 10 ns +1 delta cycles. At +2 delta cycles, Sig2 gets updated, and the third process is triggered once again.

The exit statement can break out of the simple Loop, the While loop, and the For loop.

It can't break out of the "process loop", but that's just a term I invented to emphasize that the program continues from the start of the process when it reaches the end of the process. Sorry if that misled you.

A regular variable can only be declared in the declarative region of a process:

The scope of a variable is only within the process where it is declared. They don't exist outside of the context of that process.

The Sel signal is not given an initial value in the declaration. Therefore it will get the default value of all U's, meaning uninitialized. Since "UU" is not explicitly listed in any of the When choices, the when others choice will be selected which sets Output to all X's.

Unlike in most other programming languages, the return keyword is mandatory in functions in VHDL.

Example complaint from Questa/ModelSim:

In digital logic, we can assume that the clock signal has a predictable, known frequency. Measuring real-time is simply a matter of counting the number of elapsed clock periods.

For example, if the clock frequency is 100 MHz and we have counted 1000 clock periods. Then, the elapsed time must be 1000 / 100 MHz = 10 µS.

A process with a sensitivity list is equivalent to a process with a wait on statement at the end.

The third process will wake up twice.

The first time this happens, Sig1 is 1 and Sig2 is 0. The wait until Sig1 = Sig2; expression evaluates to false, and the program will continue to wait at that line.

At the next delta cycle Sig2 has changed to 1. Now the two signals are equal, and the program will reach the report statement, causing the printout to appear.

Default values are useful for decluttering code. We can selectively override the default values in the procedure call.

The For loop reverses the vector.

The 'range attribute inserts the range which the vector was declared with. In this case, 7 downto 0.

A module's inputs and outputs must be explicitly listed in the port declaration:

Using the port map instantiation, we can create an instance of such a module in a testbench or another module. This maps the module's inputs and outputs to local signals where it's being instantiated:

Impure functions can have "side effects" like reading from or writing to objects that are not given through the parameter list. Therefore, we cannot be certain that an impure function will return the same value every time it is called with the same parameters.

To create an impure function, simply write the impure keyword before the signal declaration.

Example of an impure function accessing a signal that is not on the parameter list:

If the flip-flop is of the type that is sensitive to the rising clock edge, setup time is the time before the rising edge that the input signal must not change.

Similarly, hold time is the time after the rising edge of the clock that the data input must be held stable. If the input signal changes within the setup and hold time window, the flip-flop's output will be undetermined.

The std_logic is a resolved type. If two conflicting drivers exist, the value will be resolved according to the resolution table. The 'X' value means that the value is unknown, typically because of multiple conflicting drivers.

This is what Slv looks like in the waveform:

A procedure can contain Wait statements. That is one of the reasons why they are often used in testbenches.

Procedure parameters can be constants, signals, or variables. Signal or variable parameters can have any direction (modes); in, out, or inout.

A function must always terminate with a return keyword, and the return value is mandatory. Procedures may also contain return statements, but only without a return value.

Values can be returned from a procedure using output parameters:

A concurrent statement is a signal assignment outside of a process. The concurrent statement below, the process with a wait on statement at the end, and the process with a sensitivity list are equivalent.

There are many ways to do things in VHDL 🙂

Generics behave like constants within the module. The value of constants are defined at compile time. By adding a generic port to a module, we can make things like bit widths or the basic behavior configurable, allowing us to create instances of the same module with smaller variations.