Basic VHDL quiz - All questions

Basic VHDL - All questions

Have fun and learn from this VHDL and FPGA design quiz with 28 questions for beginners and intermediate learners in random order.

All questions include an explanation for the correct answer that will be shown after you make your selection.

You should be able to answer most of them after taking VHDLwhiz's free Basic VHDL Tutorials course.

1 / 28

What will this code print out?

2 / 28

Which statement describes a fundamental flaw in this fire control system?

3 / 28

What will this code print out?

4 / 28

Which is equivalent to this concurrent process?

5 / 28

Which statement about functions is true?

6 / 28

What will this code print out?

7 / 28

Which process is equivalent to this one?

8 / 28

How much simulation time does the For loop take?

9 / 28

Is the use of exit; in this process legal?

10 / 28

Where can a regular variable be declared in this code?

11 / 28

What will this code print out?

12 / 28

How are impure functions different from pure functions?

13 / 28

What is the value of the Slv signal?

14 / 28

Why do we normally not think about setup and hold time when designing in VHDL?

15 / 28

How do we measure real-time in an FPGA by using VHDL?

16 / 28

How many times will this process print "Haha!"?

17 / 28

What is wrong with this process?

18 / 28

Which statement is true about the signed type?

19 / 28

How will values that are passed through the generic map appear in the module?

20 / 28

How many times will the value of i be printed?

21 / 28

What is true regarding the := 0 in this procedure declaration?

22 / 28

What will this code print out?

23 / 28

What is the value of the Slv signal?

24 / 28

Which statement is correct regarding these snippets?

25 / 28

What does "setup time" for a flip-flop mean?

26 / 28

Which is true about the port declaration?

27 / 28

Which statement is true

28 / 28

What value will Output have after running this code?

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