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Basic VHDL quiz
Have fun and learn from this VHDL and FPGA design quiz with 28 questions for beginners and intermediate learners in random order.
All questions include an explanation for the correct answer that will be shown after you make your selection.
Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.
I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.
This will infer a latch:
process(InSig) is begin if InSig = '0' then OutSig <= '1'; end if; end process;This shouldn’t create any latches:
process(InSig) is begin OutSig <= '0'; if InSig = '0' then OutSig <= '1'; end if; end process;A link to the question:
https://vhdlwhiz.com/wp-content/uploads/2017/09/quiz_part-2-q6.png
Hi sir, You designed this course very well and advanced. I am happy to recommend this course to my friends.
I’m glad you enjoyed it! And thanks for taking the time to leave a nice comment.