Test your coding skills with this VHDL quiz after completing tutorials 6-11 from the Basic VHDL Tutorial series!

If you read the blog posts, watched the videos, and did the exercises you should be qualified to answer most of the questions in the quiz. The quiz is intentionally made a little bit challenging. If you don’t know the answer, try to use your reasoning skills to figure out the most likely answer.

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The std_logic_vector type can be used for creating signal buses in VHDL. The std_logic is the most commonly used type in VHDL, and the std_logic_vector is the array version of it.

While the std_logic is great for modeling the value that can be carried by a single wire, it’s not very practical for implementing collections of wires going to or from components. The std_logic_vector is a composite type, which means that it’s a collection of subelements.

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The most common type used in VHDL is the std_logic. Think of this type as a single bit, the digital information carried by a single physical wire. The std_logic gives us a more fine-grained control over the resources in our design than the integer type, which we have been using in the previous tutorials.

Normally, we want a wire in a digital interface to have either the value ‘1’ or ‘0’. These two values are the only values that a bit,

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You should always use a sensitivity list to trigger processes in production modules. Sensitivity lists are parameters to a process which lists all the signals that the process is sensitive to. If any of the signals change, the process will wake up, and the code within it is executed.

We’ve already learned to use the wait on and wait until statements for waking up a process when a signal changes. However,

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In the previous tutorial we used a conditional expression with the Wait Until statement. The expression ensured that the process was only triggered when the two counter signals where equal. But what if we wanted the program in a process to take different actions based on different inputs?

The If-Then-Elsif-Else statements can be used to create branches in our program. Depending on the value of a variable, or the outcome of an expression,

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In the previous tutorial we learned the main differences between signals and variables. We learned that signals have a broader scope than variables, which are only accessible within one process. So how can we use signals for communication between several processes?

We have already learned to use wait; to wait intinitely, and wait for to wait for a specific amount of time. There exists two more types of wait statements in VHDL.

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In the previous tutorial we learned how to declare a variable in a process. Variables are good for creating algorithms within a process, but they are not accessible to the outside world. If a scope of a variable is only within a single process, how can it interact with any other logic? The solution for this is a signal.

Signals are declared between the architecture <architecture_name> of <entity_name>

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So you have completed the first part of the Basic VHDL Tutorial series. Congratulations! You are only hours and hours and hours away from becoming a genuine VHDL whiz. But you have completed the first step, and that’s the most important part right now!

Before we go any further, you should put your skills to the test with this quiz:

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In the previous tutorial we learned how to use a For-Loop to iterate over an integer range. But what if we want a more detailed control of the loop than just a fixed integer range? We can use a While-Loop for this.

The While-Loop will continue to iterate over the enclosed code as long as the expression it tests for evaluates to true. Therefore, the While-Loop is suitable for situations where you don’t know exactly how many iteration will be needed in advance.

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In the previous tutorial we learned to create an infinite loop by using the loop statement. We also learned how the break out of a loop by using the exit statement. But what if we want the loop to iterate a certain number of times? The For-Loop is the easiest way to accomplish this.

The For-Loop allows you to iterate over a fixed range of integers or enumerated items. The item belonging to the current iteration will be available within the loop through an implicitly declared constant.

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