VHDLwhiz Membership
$39This subscription-based training program supports you in becoming successful in VHDL design. Join the community and build your confidence as an FPGA engineer.
Showing 1–12 of 16 results
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Course: Transaction-level BFM design in VHDL using Python and AI
Create a bus functional model (BFM) for a VHDL module with multiple configuration options. Learn to make a system that generates custom BFMs for any interface variant the DUT can have.
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Course: Snake game on FPGA: Real-time VHDL simulation with GUI
Implement the classic Snake game on an FPGA with a 128×32 OLED display. Create a custom GUI to play the game in real-time using the Questa VHDL simulator.
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Course: Functional coverage-driven VHDL testbench using UVVM
Learn to implement constrained random testing methods with the UVVM VHDL verification framework. Create self-checking testbenches that discover more corner case bugs.
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Course: Signal guards and delays in VHDL
Learn to use guarded blocks to disconnect signal drivers conditionally, and VHDL features like postponed processes and delay modeling mechanisms.
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Course: Pmod OLED controller: Display text and graphics with an FPGA
Connect an LED panel to your FPGA design to show messages or images. See how to read pixel data from a file into block RAM using VHDL.
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Course: Cocotb introduction
Write testbenches in Python for your VHDL design with the Cocotb hardware verification framework. Learn to use Python’s asynchronous constructs in the Questa and GHDL simulators.
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Course: RISC-V processor Hello World! in VHDL
Create a reduced instruction set computer using the RISC-V processor architecture. Learn how a CPU works by implementing one in VHDL and running it on the FPGA.
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Course: MicroBlaze SoC design
$59Learn how to build a system-on-chip (SoC) design by using a MicroBlaze soft-core processor, existing IP cores, and custom VHDL modules.
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Course: I²S audio codec ADC/DAC interface using VHDL and the Xilinx Zynq FPGA
Learn to implement the I²S protocol in VHDL and configure the ADAU1761 ADC/DAC audio codec chip on the Xilinx Zedboard with bare-metal C programming.
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Course: Combining VHDL frameworks: VUnit, UVVM, and OSVVM
You don’t have to use only one VHDL verification framework. We can pick and choose the features we need and combine them to create awesome testbenches.
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Course: VUnit for structured testbench and advanced BFM design
$59Learn to create neat testbenches and verification components using this testing framework’s VHDL libraries. Automate your simulation flow with VUnit’s Python test runner.
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