VHDL package: Binary file reader/writer
$29These VHDL packages provide a user-friendly interface for binary file access in simulation to read or write bit vectors of any length.
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VHDL package: WAV audio file reader/writer
$29These VHDL packages read and write WAV audio files. They provide a user-friendly way to run VHDL simulations on audio processing modules.
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VHDL module: AXI-style UART
$15This project contains three general-purpose, AXI compatible, universal asynchronous receiver-transmitter (UART) modules.
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VHDL package: Generic list of protected type
$15This VHDL package can store any data type in dynamic memory. It mimics the behavior of Python’s list class and supports negative indexing.
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