VHDL debouncer – single switch or multiple bits
$0This VHDL project contains three modules that can debounce a switch or a button or arrays of them using a generate statement.
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VHDL linked list protected type
$0This VHDL package contains an object-oriented linked list of protected type that implements a dynamic length FIFO for use in testbenches.
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VHDL ring buffer FIFO in block RAM
$0This VHDL implementation of a ring buffer FIFO has generic data width and depth settings.
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VHDL AXI FIFO using block RAM
$0This VHDL implementation of an AXI-style FIFO has generic data width and depth settings.
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