VHDL dual 7-segment display controller
$0This VHDL module shows a decimal value from 0 to 99 on the Pmod SSD: Seven-segment Display from Digilent or similar dual 7-segment display.
Showing 49–53 of 53 results
-
-
VHDL debouncer – single switch or multiple bits
$0This VHDL project contains three modules that can debounce a switch or a button or arrays of them using a generate statement.
-
VHDL linked list protected type
$0This VHDL package contains an object-oriented linked list of protected type that implements a dynamic length FIFO for use in testbenches.
-
VHDL ring buffer FIFO in block RAM
$0This VHDL implementation of a ring buffer FIFO has generic data width and depth settings.
-
VHDL AXI FIFO using block RAM
$0This VHDL implementation of an AXI-style FIFO has generic data width and depth settings.
End of content
End of content