I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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What is VHDL?
In short, VHDL is a computer language used for designing digital circuits. I use the term “computer language” to distinguish VHDL from other, more common programming languages like Java or C++. But is VHDL a programming language? Yes, it is. It’s a programming language that is of no use when it comes to creating computer…
Basic VHDL quiz – Part 4
Test your progress with this VHDL quiz after completing part 4 of the Basic VHDL Tutorial series!
How to use Loop and Exit in VHDL
In the previous tutorial we learned how to delay time using the wait for statement. We also learned about the process loop. We now know that if we let it, the process “thread” will loop within the process forever. But what if we want to do something just once at the beginning of the process?…
BMP file bitmap image read using TEXTIO
Converting the image file to a bitmap format makes for the easiest way to read a picture using VHDL. Support for the BMP raster graphics image file format is built into the Microsoft Windows operating system. That makes BMP a suitable image format for storing photos for use in VHDL testbenches. In this article, you…
How to stop simulation in a VHDL testbench
How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run. The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving…