The leftmost bit of signed types is the sign bit. If it's '1', the number is negative. If it's '0', the number is positive. Because one bit is used for the sign bit, signed types cannot represent as high values as an unsigned type with the same bit length:

A concurrent statement is a signal assignment outside of a process. The concurrent statement below, the process with a wait on statement at the end, and the process with a sensitivity list are equivalent.

There are many ways to do things in VHDL 🙂

The Sel signal is not given an initial value in the declaration. Therefore it will get the default value of all U's, meaning uninitialized. Since "UU" is not explicitly listed in any of the When choices, the when others choice will be selected which sets Output to all X's.

A module's inputs and outputs must be explicitly listed in the port declaration:

Using the port map instantiation, we can create an instance of such a module in a testbench or another module. This maps the module's inputs and outputs to local signals where it's being instantiated:

Generics behave like constants within the module. The value of constants are defined at compile time. By adding a generic port to a module, we can make things like bit widths or the basic behavior configurable, allowing us to create instances of the same module with smaller variations.

If the flip-flop is of the type that is sensitive to the rising clock edge, setup time is the time before the rising edge that the input signal must not change.

Similarly, hold time is the time after the rising edge of the clock that the data input must be held stable. If the input signal changes within the setup and hold time window, the flip-flop's output will be undetermined.

We don't have to think about setup and hold time inside of the FPGA because this is handled automatically by the software tools in a later process called place and route.

However, you will have to consider setup and time constraints when interfacing external devices. Then you may have to design your VHDL code to avoid setup and hold time violations on the external interface.