I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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How to use Signed and Unsigned in VHDL
The signed and unsigned types in VHDL are bit vectors, just like the std_logic_vector type. The difference is that while the std_logic_vector is great for implementing data buses, it’s useless for performing arithmetic operations. If you try to add any number to a std_logic_vector type, ModelSim will produce the compilation error: No feasible entries for…
How to stop simulation in a VHDL testbench
How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run. The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving…
How to create your first VHDL program: Hello World!
When learning a new programming language, I always like to start by learning how to print. When you master outputting “Hello World!”, you know that you’ve got the environment working. It also shows you the basic skeleton of the language, the bare minimum code required to produce any output. You might be thinking: but VHDL…
Should I learn VHDL if Verilog is becoming more popular?
Which HDL is the most popular, and should I learn VHDL or Verilog? That’s a question I often get asked, and it’s understandable. People want to future-proof their learning by betting on the winning horse. But which one is it, and does it matter?
An Introduction to FPGAs & Programmable Logic
This video is an introductory presentation about FPGA and programmable logic technology. I delivered this 45 minutes talk at an event hosted by 7 Peaks Software in Bangkok, Thailand, on November 19th, 2019.
How to use constants and Generic Map in VHDL
Creating modules is a great way to reuse code, but often you need the same module with smaller variations throughout your design. This is what generics and the generic map are for. It allows you to make certain parts of the module configurable at compile-time. Constants are used when we want to avoid typing the…
Dear Jonas
Thanks for the content, thumbs up. please keep up the good work!
Best Regards
Thanks! That’s good to hear.
You are doing a very nice job. Top quality!
Thanks! I really appreciate your comment.
Hello Jonas
You really did save me by these great videos and materials.
These tutorials are the best thing on the internet.
Thank you for creating them.
Thanks! That’s encouraging to hear. I will do my best to keep up the quality of my blog posts.
Thank you so much man you are awesome! i learnt vhdl in university but i forgot after all years. i started again working. You help me too much! i will continue to course after this beginner course. i am planning the begin beginner fast track ! please dont stop the teaching us . thank you so much! greetings from turkey 🙂
Hello, Utku. Thank you for the nice comment! I’m glad you found my blog to be helpful. I will keep the free and premium content coming your way.
Thank you for providing such great content on a subject that imo can be tricky to really understand. But you make it easy for everyone!
That’s great to hear! I will keep on creating tutorials and articles for you. ?
Dear Jonas,
I’m an electronic engineer from Morocco, currently studying for a masters degree in microelectronics and sensors in France.
You helped me a lot to remember some of the vhdl basics and get more further into it.
I worked on an academic project using basys3 and vivado for a vga controller.
Thank you very much for this great content, keep up the good work.
I’m glad you like the quiz. It’s a good way to refresh your knowledge. 🙂
Excellent learning tool
Thanks! By the way, I also use quizzes in the VHDLwhiz membership.
Great tutorials! Short and sweet!
I’ll be sure to go onto the FPGA and VHDL Fast-Track after completing the basic tutorials..
Thanks, Dale! Also, check out the VHDLwhiz Membership, which gives you multiple courses, resource items, and coding challenges and supports your success in FPGA design.
Nice quiz, only problem is sharing your score on facebook is not working.
Thanks for the feedback. I’ve created a task on this. I’ll see if I can fix it when I have the time.