Course: I²S audio codec ADC/DAC interface using VHDL and the Xilinx Zynq FPGA
$59Learn to implement the I²S protocol in VHDL and configure the ADAU1761 ADC/DAC audio codec chip on the Xilinx Zedboard with bare-metal C programming.
Everything that uses FPGA boards or pluggable Pmod modules from Digilent.
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Learn to implement the I²S protocol in VHDL and configure the ADAU1761 ADC/DAC audio codec chip on the Xilinx Zedboard with bare-metal C programming.

Learn to create an I²C controller (master) in VHDL and communicate with the Digilent Pmod RTCC: Real-time Clock / Calendar module.
Learn to create an SPI master in VHDL for reading an ambient light sensor from an FPGA. We also make an SPI slave BFM for simulating the ADC chip.
FPGA projects are challenging to debug, and that’s because it’s hard to understand what’s going on in the design. But once we gain insight and see the complete picture, problems often melt away.
Learn to use Xilinx’s MMCMs to derive clocks, create a gated clock, and write a run-time configurable clock divider without sacrificing timing using the BUFGCE primitive.

Hands-On for Absolute Beginners. Understand the basics of FPGA development using VHDL in a few evenings!

This project contains three general-purpose, AXI compatible, universal asynchronous receiver-transmitter (UART) modules.

This VHDL module shows a decimal value from 0 to 99 on the Pmod SSD: Seven-segment Display from Digilent or similar dual 7-segment display.
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