I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
Similar Posts
How to make ModelSim from Quartus Prime Lite work on Ubuntu 20.04
The ModelSim version that comes with Intel Quartus Prime Lite Edition is a good alternative if you want to try out VHDL simulation on your home computer. The software is available for both Windows and Linux, but Intel only supports Red Hat-based distros like CentOS Linux. Fortunately, you are just a few hacks away from…
std_logic vs std_ulogic
VHDL includes few built-in types but offers several additional types through extension packages. Two of the most widely used types are std_logic and std_ulogic. The difference between them is that the former is resolved while the latter isn’t. Before we go on to investigate what it means that a type is resolved, let’s first look…
How to create a self-checking testbench
A self-checking testbench is a VHDL program that verifies the correctness of the device under test (DUT) without relying on an operator to manually inspect the output. The self-checking testbench runs entirely on its own, and prints an “OK” or “Failed” message in the end. Every VHDL module should have an associated self-checking testbench. It’s…
How to create a concurrent statement in VHDL
A concurrent statement in VHDL is a signal assignment within the architecture, but outside of a normal process construct. The concurrent statement is also referred to as a concurrent assignment or concurrent process. When you create a concurrent statement, you are actually creating a process with certain, clearly defined characteristics. Concurrent statements are always equivalent…
How a signal is different from a variable in VHDL
In the previous tutorial we learned how to declare a variable in a process. Variables are good for creating algorithms within a process, but they are not accessible to the outside world. If a scope of a variable is only within a single process, how can it interact with any other logic? The solution for…
How to use Wait On and Wait Until in VHDL
In the previous tutorial we learned the main differences between signals and variables. We learned that signals have a broader scope than variables, which are only accessible within one process. So how can we use signals for communication between several processes? We have already learned to use wait; to wait infinitely, and wait for to…
Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.
I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.
This will infer a latch:
This shouldn’t create any latches:
A link to the question:
https://vhdlwhiz.com/wp-content/uploads/2017/09/quiz_part-2-q6.png
Hi sir, You designed this course very well and advanced. I am happy to recommend this course to my friends.
I’m glad you enjoyed it! And thanks for taking the time to leave a nice comment.