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Test your progress with this VHDL quiz after completing tutorials 12-17 from the Basic VHDL Tutorial series!
Logic gates interactive demo
The basic logic gates NOT, AND, NAND, OR, NOR, XOR, and XNOR are fundamental building blocks in digital circuits corresponding to Boolean operators.
Play with the switches to see how the outputs change! 😀
How to use the most common VHDL type: std_logic
The most common type used in VHDL is the std_logic. Think of this type as a single bit, the digital information carried by a single physical wire. The std_logic gives us a more fine-grained control over the resources in our design than the integer type, which we have been using in the previous tutorials. Normally,…
Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.
I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.
This will infer a latch:
process(InSig) is begin if InSig = '0' then OutSig <= '1'; end if; end process;This shouldn’t create any latches:
process(InSig) is begin OutSig <= '0'; if InSig = '0' then OutSig <= '1'; end if; end process;A link to the question:
https://vhdlwhiz.com/wp-content/uploads/2017/09/quiz_part-2-q6.png
Hi sir, You designed this course very well and advanced. I am happy to recommend this course to my friends.
I’m glad you enjoyed it! And thanks for taking the time to leave a nice comment.