The initial value of MySignal is 0.

The For loop will execute the MySignal <= MySignal + 1; line 10 times.

Signal values only become effective when the process pauses, for example, at a Wait statement. There is no Wait statement in the For loop or before the report statement. Therefore, the value of MySignal is still 0 when the report statement is executed.

The MySignal <= MySignal + 1; line schedules a new value onto MySignal, its old value plus 1. There is no Wait statement inside of the For loop. Therefore, the signal's value doesn't get updated between the 10 iterations.

Signal values are scheduled for the next time step. If there are several assignments before the next timestep, the last assignment "wins".

The wait for 0 ns; line causes MySignal to update its value before the report statement and the value 1 is printed. Waiting for 0 nanoseconds is a common trick in VHDL for updating signal values without letting any simulation time pass.

The For loop iterates 10 times. The wait for 0 ns; line directly after the signal assignment ensures that its value is updated between each iteration.

At 10 nanoseconds the first process will change the Sig1 signal. This will trigger the second process to wake up and change Sig2.

The third process is sensitive the both Sig1 and Sig2. When either of them changes, the process will wake up and the printout will appear.

Even if everything happens at exactly 10 ns simulation time, the third process will be woken up twice, once by each of the signals. This is not an error. It happens because the VHDL simulator operates with event scheduling timesteps called delta cycles.

When the first process changes Sig1 it causes the other two processes to wake up simultaneously at 10 ns +1 delta cycles. At +2 delta cycles, Sig2 gets updated, and the third process is triggered once again.

The third process will wake up twice.

The first time this happens, Sig1 is 1 and Sig2 is 0. The wait until Sig1 = Sig2; expression evaluates to false, and the program will continue to wait at that line.

At the next delta cycle Sig2 has changed to 1. Now the two signals are equal, and the program will reach the report statement, causing the printout to appear.

The two code snippets do exactly the same thing. Use whichever one you like.

A process with a sensitivity list is equivalent to a process with a wait on statement at the end.

The std_logic is a resolved type. If two conflicting drivers exist, the value will be resolved according to the resolution table. The 'X' value means that the value is unknown, typically because of multiple conflicting drivers.

This is what Slv looks like in the waveform:

The For loop reverses the vector.

The 'range attribute inserts the range which the vector was declared with. In this case, 7 downto 0.