I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
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Generate statement debouncer example
The generate statement in VHDL can automatically duplicate a block of code to closures with identical signals, processes, and instances. It’s a for loop for the architecture region that can create chained processes or module instances.
How to use conditional statements in VHDL: If-Then-Elsif-Else
In the previous tutorial we used a conditional expression with the Wait Until statement. The expression ensured that the process was only triggered when the two counter signals where equal. But what if we wanted the program in a process to take different actions based on different inputs? The If-Then-Elsif-Else statements can be used to…
How to create a Tcl-driven testbench for a VHDL code lock module
Most VHDL simulators use the Tool Command Language (Tcl) as their scripting language. When you type a command in the console of the simulator, you are using Tcl. Furthermore, you can create scripts with Tcl that run in the simulator and interact with your VHDL code. In this article, we will create a self-checking testbench…
An Introduction to FPGAs & Programmable Logic
This video is an introductory presentation about FPGA and programmable logic technology. I delivered this 45 minutes talk at an event hosted by 7 Peaks Software in Bangkok, Thailand, on November 19th, 2019.
How to create a PWM controller in VHDL
Pulse-width modulation (PWM) is an efficient way to control analog electronics from purely digital FPGA pins. Instead of attempting to regulate the analog voltage, PWM rapidly switches on and off the supply current at full power to the analog device. This method gives us precise control over the moving average of energy provided to the…
BMP file bitmap image read using TEXTIO
Converting the image file to a bitmap format makes for the easiest way to read a picture using VHDL. Support for the BMP raster graphics image file format is built into the Microsoft Windows operating system. That makes BMP a suitable image format for storing photos for use in VHDL testbenches. In this article, you…
Dear Jonas
Thanks for the content, thumbs up. please keep up the good work!
Best Regards
Thanks! That’s good to hear.
You are doing a very nice job. Top quality!
Thanks! I really appreciate your comment.
Hello Jonas
You really did save me by these great videos and materials.
These tutorials are the best thing on the internet.
Thank you for creating them.
Thanks! That’s encouraging to hear. I will do my best to keep up the quality of my blog posts.
Thank you so much man you are awesome! i learnt vhdl in university but i forgot after all years. i started again working. You help me too much! i will continue to course after this beginner course. i am planning the begin beginner fast track ! please dont stop the teaching us . thank you so much! greetings from turkey 🙂
Hello, Utku. Thank you for the nice comment! I’m glad you found my blog to be helpful. I will keep the free and premium content coming your way.
Thank you for providing such great content on a subject that imo can be tricky to really understand. But you make it easy for everyone!
That’s great to hear! I will keep on creating tutorials and articles for you. ?
Dear Jonas,
I’m an electronic engineer from Morocco, currently studying for a masters degree in microelectronics and sensors in France.
You helped me a lot to remember some of the vhdl basics and get more further into it.
I worked on an academic project using basys3 and vivado for a vga controller.
Thank you very much for this great content, keep up the good work.
I’m glad you like the quiz. It’s a good way to refresh your knowledge. 🙂
Excellent learning tool
Thanks! By the way, I also use quizzes in the VHDLwhiz membership.
Great tutorials! Short and sweet!
I’ll be sure to go onto the FPGA and VHDL Fast-Track after completing the basic tutorials..
Thanks, Dale! Also, check out the VHDLwhiz Membership, which gives you multiple courses, resource items, and coding challenges and supports your success in FPGA design.
Nice quiz, only problem is sharing your score on facebook is not working.
Thanks for the feedback. I’ve created a task on this. I’ll see if I can fix it when I have the time.