I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
Similar Posts
Using Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO)
This tutorial covers using the Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO) cores to debug and monitor your VHDL design in the Xilinx Vivado IDE. In many cases, designers are in need to perform on-chip verification. That is, gaining access to an internal signal’s behavior in their FPGA design for verification purposes. One option…
Dual 7-segment display FPGA controller
In this article, I will present a VHDL module that can display a two-digit number on the Pmod SSD: Seven-segment Display from Digilent. The dual 7-segment display is compatible with the Pmod interface, meaning that you can use it without any soldering. It fits into the Pmod connector, which is standard on many FPGA development boards.
How to use constants and Generic Map in VHDL
Creating modules is a great way to reuse code, but often you need the same module with smaller variations throughout your design. This is what generics and the generic map are for. It allows you to make certain parts of the module configurable at compile-time. Constants are used when we want to avoid typing the…
How to initialize RAM from file using TEXTIO
A convenient way to populate block RAM with initial values is to read binary or hexadecimal literals from an ASCII file. This is also a good way to create a ROM (read-only memory) in VHDL. After all, RAM and ROM are the same thing in FPGAs, ROM is a RAM that you only read from….
How to use a While loop in VHDL
In the previous tutorial, we learned how to use a For-Loop to iterate over an integer range. But what if we want a more detailed control of the loop than just a fixed integer range? We can use a While-Loop for this. The While-Loop will continue to iterate over the enclosed code as long as…
How to use Loop and Exit in VHDL
In the previous tutorial we learned how to delay time using the wait for statement. We also learned about the process loop. We now know that if we let it, the process “thread” will loop within the process forever. But what if we want to do something just once at the beginning of the process?…
Dear Jonas
Thanks for the content, thumbs up. please keep up the good work!
Best Regards
Thanks! That’s good to hear.
You are doing a very nice job. Top quality!
Thanks! I really appreciate your comment.
Hello Jonas
You really did save me by these great videos and materials.
These tutorials are the best thing on the internet.
Thank you for creating them.
Thanks! That’s encouraging to hear. I will do my best to keep up the quality of my blog posts.
Thank you so much man you are awesome! i learnt vhdl in university but i forgot after all years. i started again working. You help me too much! i will continue to course after this beginner course. i am planning the begin beginner fast track ! please dont stop the teaching us . thank you so much! greetings from turkey 🙂
Hello, Utku. Thank you for the nice comment! I’m glad you found my blog to be helpful. I will keep the free and premium content coming your way.
Thank you for providing such great content on a subject that imo can be tricky to really understand. But you make it easy for everyone!
That’s great to hear! I will keep on creating tutorials and articles for you. ?
Dear Jonas,
I’m an electronic engineer from Morocco, currently studying for a masters degree in microelectronics and sensors in France.
You helped me a lot to remember some of the vhdl basics and get more further into it.
I worked on an academic project using basys3 and vivado for a vga controller.
Thank you very much for this great content, keep up the good work.
I’m glad you like the quiz. It’s a good way to refresh your knowledge. 🙂
Excellent learning tool
Thanks! By the way, I also use quizzes in the VHDLwhiz membership.
Great tutorials! Short and sweet!
I’ll be sure to go onto the FPGA and VHDL Fast-Track after completing the basic tutorials..
Thanks, Dale! Also, check out the VHDLwhiz Membership, which gives you multiple courses, resource items, and coding challenges and supports your success in FPGA design.
Nice quiz, only problem is sharing your score on facebook is not working.
Thanks for the feedback. I’ve created a task on this. I’ll see if I can fix it when I have the time.