Test your coding skills with this VHDL quiz after completing tutorials 6-11 from the Basic VHDL Tutorial series!

If you read the blog posts, watched the videos, and did the exercises you should be qualified to answer most of the questions in the quiz. The quiz is intentionally made a little bit challenging. If you don’t know the answer, try to use your reasoning skills to figure out the most likely answer.

Read the explanations that come after each answer, there’s some micro-learning in there.

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Basic VHDL Quiz - part 2 I got %%score%% of %%total%% right
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Author: Jonas Julian Jensen

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

## 4 thoughts on “Basic VHDL Quiz – part 2”

1. Though those two codes are logically equivalent, the right one infers a transparent latch, it shouldn’t be used for synthesis.

Posted on September 15, 2017 at 4:25 pm
1. I don’t think it does, but I’m not 100% sure what the synthesis tools do all the time.

This will infer a latch:

process(InSig) is
begin
if InSig = '0' then
OutSig <= '1';
end if;
end process;


This shouldn’t create any latches:

process(InSig) is
begin
OutSig <= '0';
if InSig = '0' then
OutSig <= '1';
end if;
end process;