Open Logic – An FPGA Standard Library
What is Open Logic? It is an open-source VHDL library that can save you time and help you avoid vendor lock-in. Read the article written by its creator to learn more!
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ASCII table
VHDL has a built-in character type that can represent ASCII and Latin-1 characters. It’s in the standard (STD) library, which is loaded by default. You don’t need to import it. Below, you can find the character type definition from the Language Reference Manual (LRM) and tables that list and explain all 256 values. ASCII (0-127)…
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Logic gates interactive demo
The basic logic gates NOT, AND, NAND, OR, NOR, XOR, and XNOR are fundamental building blocks in digital circuits corresponding to Boolean operators.
Play with the switches to see how the outputs change! 😀
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Basic VHDL quiz
Have fun and learn from this VHDL and FPGA design quiz with 28 questions for beginners and intermediate learners in random order.
All questions include an explanation for the correct answer that will be shown after you make your selection.
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Part 6: Complementary FIR filters
This article is by guest author Dimitar Marinov, whom I (Jonas) contacted after seeing his excellent videos about DSP filters. You can read more about Dimitry below the blog post and find a link to his YouTube channel here. But first, read on to learn about complementary finite impulse response (FIR) filters!
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Part 5: Polyphase FIR filters
Polyphase filters are a class of specialized filters used in sample rate conversion. Whereas most FIR filters have one delay line, Polyphase filters have multiple. To understand the logic behind this, we’ll first have to dive into the topic of sample rate conversion.
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Part 4: FIR filter testing
So far, the spotlight has fallen over the FIR filter design and its various forms. However, there is a problem that is just as important – how to ensure the implementation is working correctly. Whereas there are some standard techniques, it’s not always clear whether the design is error-proof. Therefore, this post discusses the most essential testing procedures and introduces a verification method that can easily incorporate them.
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Should I learn VHDL if Verilog is becoming more popular?
Which HDL is the most popular, and should I learn VHDL or Verilog? That’s a question I often get asked, and it’s understandable. People want to future-proof their learning by betting on the winning horse. But which one is it, and does it matter?
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Function and procedure call overhead in VHDL
There are controversies in the VHDL community about how you can and shouldn’t use subprograms. Some say you should avoid using functions or procedures in synthesizable (RTL) code. While there are debatable subjective reasons to restrict the use of subprograms, many of these beliefs stem from myths or misconceptions. Therefore, I’m writing this article to…
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How the AXI-style ready/valid handshake works
The ready/valid hardware data transfer protocol is simple and ingenious, providing flow control with only two control signals. The rules are straightforward: data transfer only happens when both ready and valid are ‘1’ during the same clock cycle.
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