Free VHDL simulators

Free VHDL simulator alternatives

Professional VHDL simulators are more expensive than most individuals can afford. But fortunately, there are many free and legal alternatives that you can download and install.

Microsoft Windows is the easiest to install on, but many simulators also have a Linux version. FPGA vendors usually only support the Red Hat Linux distribution. But with a little effort, you can make it work in other distros, including Ubuntu.

Mac OS is the most challenging platform because there’s only one open-source simulator that works natively.

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List of four text strings on paper

How to create a list of strings in VHDL

Text strings in VHDL are generally limited to fixed-length character arrays. That makes sense because VHDL describes hardware, and generic-length strings require dynamic memory.

To define an array of strings, you have to allocate space at compile-time for the highest number of strings you want to store. And even worse, you must decide on the strings’ max length and pad every occurrence to that number of characters. The code below shows an example usage of such a construct.

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IC sockets illustrating VHDL configurations

Configuration constructs explained

This article examines how we can use configuration constructs to create variants of a module or testbench without maintaining multiple versions of the file. We will also look at other use cases for configuration declarations in VHDL design.

Configurations have been part of the VHDL standard since the first version of the language. But still, many FPGA designers never use them, perhaps because few people understand how configurations work.

I find that unfortunate because it’s really not that complicated.

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VHDL instantiation

Entity instantiation and component instantiation

There are two ways to instantiate a module in VHDL: component instantiation and entity instantiation. Some people refer to the latter as direct instantiation.

Entity instantiation didn’t exist in the first revisions VHDL, but it has been available since VHDL’93. This is the method that I recommend unless you have specific reasons to use component instantiation.

To use the component instantiation method, you first have to declare the component in the declarative scope of where you want the module instance.

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The Lattice iCEstick FPGA board controlling a TowerPro SG90 servo

RC servo controller using PWM from an FPGA pin

Radio-controlled (RC) model servos are tiny actuators typically used in hobbyist model planes, cars, and boats. They allow the operator to control the vehicle via a radio link remotely. Because RC models have been around for a long time, the de-facto standard interface is pulse-width modulation (PWM), rather than a digital scheme.

Fortunately, it’s easy to implement PWM with the precise timing that an FPGA can exert on its output pins. In this article,

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Digital code lock

How to create a Tcl-driven testbench for a VHDL code lock module

Most VHDL simulators use the Tool Command Language (Tcl) as their scripting language. When you type a command in the console of the simulator, you are using Tcl. Furthermore, you can create scripts with Tcl that run in the simulator and interact with your VHDL code.

In this article, we will create a self-checking testbench that used Tcl instead of VHDL to verify that a VHDL module behaves correctly.

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How to Stop Simulation in a VHDL Testbench

How to stop simulation in a VHDL testbench

How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run.

The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving Tcl, I will list the commands for the ModelSim and Vivado simulators.

You can download an example project with the four different testbenches from this article if you have ModelSim installed.

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(clk'event and clk = '1') vs rising_edge(clk)

Clk’event vs rising_edge

When you have worked with VHDL code written by many other FPGA engineers, you are bound to notice that there are two common ways to model an edge detector in VHDL. There’s the rising_edge(clk) statement, and there’s the old style clk’event and clk = ‘1’ method.

The two if-statements do the same thing once the code is on the FPGA. They postulate that whatever is inside of the if-statement happens on the rising edge of the trigger signal,

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