Function and procedure call overhead in VHDL

Function and procedure call overhead in VHDL

There are controversies in the VHDL community about how you can and shouldn’t use subprograms. Some say you should avoid using functions or procedures in synthesizable (RTL) code. While there are debatable subjective reasons to restrict the use of subprograms, many of these beliefs stem from myths or misconceptions. Therefore, I’m writing this article to…

The ModelSim commands you need to know

The ModelSim commands you need to know

Many people struggle to understand the ModelSim/QuestaSim VHDL simulator’s workflow. I think that’s unnecessary because the basic workflow isn’t hard to learn. I regard the graphical user interface (GUI) as a front-end for the commands listed in this article. For example, when you click the Compile button in the ModelSim GUI, it runs the vcom…

Free VHDL simulator alternatives

Free VHDL simulator alternatives

Professional VHDL simulators are more expensive than most individuals can afford. But fortunately, there are many free and legal alternatives that you can download and install. Microsoft Windows is the easiest to install on, but many simulators also have a Linux version. FPGA vendors usually only support the Red Hat Linux distribution. But with a…

How to create a list of strings in VHDL

How to create a list of strings in VHDL

Text strings in VHDL are generally limited to fixed-length character arrays. That makes sense because VHDL describes hardware, and generic-length strings require dynamic memory. To define an array of strings, you have to allocate space at compile-time for the highest number of strings you want to store. And even worse, you must decide on the…

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