There are controversies in the VHDL community about how you can and shouldn’t use subprograms. Some say you should avoid using functions or procedures in synthesizable (RTL) code.

While there are debatable subjective reasons to restrict the use of subprograms, many of these beliefs stem from myths or misconceptions. Therefore, I’m writing this article to give you clarity and understanding of subprograms so you can decide for yourself.

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Many people struggle to understand the ModelSim/QuestaSim VHDL simulator’s workflow. I think that’s unnecessary because the basic workflow isn’t hard to learn.

I regard the graphical user interface (GUI) as a front-end for the commands listed in this article. For example, when you click the Compile button in the ModelSim GUI, it runs the vcom command back-end. The screenshot below shows the command echoed to the transcript window after we click the Compile button.

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Professional VHDL simulators are more expensive than most individuals can afford. But fortunately, there are many free and legal alternatives that you can download and install.

Microsoft Windows is the easiest to install on, but many simulators also have a Linux version. FPGA vendors usually only support the Red Hat Linux distribution. But with a little effort, you can make it work in other distros, including Ubuntu.

Mac OS is the most challenging platform because there’s only one open-source simulator that works natively.

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Text strings in VHDL are generally limited to fixed-length character arrays. That makes sense because VHDL describes hardware, and generic-length strings require dynamic memory.

To define an array of strings, you have to allocate space at compile-time for the highest number of strings you want to store. And even worse, you must decide on the strings’ max length and pad every occurrence to that number of characters. The code below shows an example usage of such a construct.

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