In digital logic, we can assume that the clock signal has a predictable, known frequency. Measuring real-time is simply a matter of counting the number of elapsed clock periods.

For example, if the clock frequency is 100 MHz and we have counted 1000 clock periods. Then, the elapsed time must be 1000 / 100 MHz = 10 µS.

A procedure can contain Wait statements. That is one of the reasons why they are often used in testbenches.

Procedure parameters can be constants, signals, or variables. Signal or variable parameters can have any direction (modes); in, out, or inout.

A function must always terminate with a return keyword, and the return value is mandatory. Procedures may also contain return statements, but only without a return value.

Values can be returned from a procedure using output parameters:

1. There is no reset of the State signal
2. Therefore, the State signal will get the default value at first
3. The default value is always the leftmost value from the type declaration
4. This causes the module to start up in the Armed state

(The ordering of the values in the t_State type declaration is also questionable. The Safe state should have been the leftmost state. Good job if you spotted that!)

Unlike in most other programming languages, the return keyword is mandatory in functions in VHDL.

Example complaint from Questa/ModelSim:

Impure functions can have "side effects" like reading from or writing to objects that are not given through the parameter list. Therefore, we cannot be certain that an impure function will return the same value every time it is called with the same parameters.

To create an impure function, simply write the impure keyword before the signal declaration.

Example of an impure function accessing a signal that is not on the parameter list:

Default values are useful for decluttering code. We can selectively override the default values in the procedure call.